Note: Pin 1 is marked for orientation.
INTERFACE SIGNAL DESCRIPTION
VCC: +5V Power Supply
VDD: +12V Power Supply
ClK (Clock, Input)
An external timing source connected to the ClK input provides
the necessary clocking.
RESET (Reset, Input)
A HIGH on this input causes initialization. Reset terminates any
operation in progress, and clears the status register to zero. The
internal stack pointer is initialized and the contents of the stack
may be affected. After a reset the END output, the ERR output
and the SVREQ output will be lOW. For proper initialization,
RESET must be HIGH for at least five ClK periods following
stable power supply voltages and stable clock.
C/O (Command/Data Select, Input)
The c/is input together with the RD and WR inputs determines the
type of transfer to be performed on the data bus as follows:
L = LOW
H = HIGH
X = DON'T CARE
Push data byte into the stack
Pop data byte from the stack
END (End of Execution, Output)
A HIGH on this output indicates that execution of the current
command is complete. This output will be cleared lOW by ac-
tivating the EACK input lOW or performing any read or write
operation or device initialization using the RESET. If EACK is tied
lOW, the END output will be a pulse (see EACK description).
Reading the status register while a command execution is in
progress is allowed. However any read or write operation clears
the flip-flop that generates the END output. Thus such continu-
ous reading could conflict with internal logic setting of the END
flip-flop at the end of command execution.
EACK (End Acknowledge, Input)
This input when lOW makes the END output go lOW. As men-
tioned earlier HIGH on the END output signals completion of a
command execution. The END signal is derived from an internal
flip-flop which is clocked at the completion of a command. This
flip-flop is clocked to the reset state when EACK is lOW. Con-
sequently, if EACK is tied lOW, the END output will be a pulse
that is approximately one ClK period wide.
SVREQ (Service Request, Output)
A HIGH on this output indicates completion of a command. In
this sense this output is the same as the END output. However,
the SVREQ output will go HIGH at the completion of a com-
mand. This bit must be 1 for SVREQ to go HIGH. The SVREQ
can be cleared (Le., go lOW) by activating the SVACK input
lOW or initializing the device using the RESET. Also, the
SVREQ will be automatically cleared after completion of any
command that has the service request bit as o.
SVACK (Service Acknowledge, Input)
A lOW on this input clears SVREQ. If the SVACK input is per-
manently tied lOW, it will conflict with the internal setting of the
SVREQ output. rhus the SVREQ indication cannot be relied
upon if the SVACK is tied lOW.
DBO-DB7 (Data Bus, Input/Output)
These eight bidirectional lines are used to transfer command,
status and operand information between the device and the host
processor. DBO is the least significant and DB7 is the most
significant bit position. HIGH on a data bus line corresponds to 1
and lOW corresponds to O.
When pushing operands on the stack using the data bus, the least
significant byte must be pushed first and most significant byte
last. When popping the stack to read the result of an operation,
the most Significant byte will be available on the data bus first and
the least significant byte will be the last. Moreover, for pushing
operands and popping results, the number of transactions must
be equal to the proper number of bytes appropriate for the chosen
format. Otherwise, the internal byte pointer will not be aligned
properly. The Am9512 single precision format requires 4 bytes
and double precision format requires 8 bytes.
ERR (Error, Output)
This output goes HIGH to indicate that the current command
execution resulted in an error condition. The error conditions
are: attempt to divide by zero, exponent overflow and exponent
underflow. The ERR output is cleared lOW on read status reg-
ister operation or upon RESET.
The ERR output is derived from the error bits in the status
register. These error bits will be updated internally at an appro-
priate time during a command execution. Thus ERR output going
HIGH may not correspond with the completion of a command.
Reading of the status register can be performed while a com-
mand execution is in progress. However it should be noted that
reading the status register clears the ERR output. Thus reading
the status register while a command execution in progress may
result in an internal conflict with the ERR output.