INTERFACE SIGNAL DESCRIPTION
VCC: +5V Power Supply
VDD: + 12V Power Supply
ClK (Clock, Input)
An external timing source connected to the ClK input provides
the necessary clocking. The ClK input can be asynchronous to
the RD and WR control signals.
RESET (Reset, Input)
A HIGH on this input causes initialization. Reset terminates any
operation in progress, and clears the status register to zero. The
internal stack pointer is initialized and the contents of the stack
may be affected but the command register is not affected by the
reset operation. After a reset the END output will be HIGH, and
the SVREQ output will be lOW. For proper initialization, the
RESET input must be HIGH for at least five ClK periods following
stable power supply voltages and stable clock.
cio (Command/Data Select, Input)
The C/O input together with the RD and WR inputs determines
the type of transfer to be performed on the data bus as follows:
C/D RD WR
Push data byte into the stack
Pop data byte from the stack
Enter command byte from the data bus
L = LOW
H = HIGH
X = DON'T CARE
END (End of Execution, Output)
A lOW on this output indicates that execution of the current
command is complete. This output will be cleared HIGH by ac-
tivating the EACK input LOW or performing any read or write
operation or device initialization using the RESET. If EACK is
tied lOW, the END output will be a pulse (see EACK descrip-
tion). This is an open drain output and requires a pull up to +5V.
Reading the status register while a command execution is in
progress is allowed. However any read or write operation clears
the flip-flop that generates the END output. Thus such continu-
ous reading could conflict with internal logic setting the END
flip-flop at the completion of command execution.
EACK (End Acknowledge, Output)
This input when LOW makes the END output go LOW. As men-
tioned earlier HIGH on the END output signals completion of a
command execution. The END output signal is derived from an
internal flip-flop which is clocked at the completion of a com-
mand. This flip-flop is clocked to the reset state when EACK is
LOW. Consequently, if the EACK is tied LOW, the END output
will be a pulse that is approximately one ClK period wide.
SVREQ (Service Request, Output)
A HIGH on this output indicates completion of a command. In
this sense this output is same as the END output. However,
whether the SVREQ output will go HIGH at the completion of a
command or not is determined by a service request bit in the
command register. This bit must be 1 for SVREQ to go HIGH.
The SVREQ can be cleared (Le., go lOW) by activating the
SVACK input lOW or initializing the device using the RESET.
Also, the SVREQ will be automatically cleared after completion
of any command that has the service request bit as O.
SVACK (Service Acknowledge, Input)
A lOW on this input activates the reset input of the flip-flop
generating the SVREQ output. If the SVACK input is perma-
nently tied LOW, it will conflict with the internal setting of the
flip-flop to generate the SVREQ output. Thus the SVREQ indi-
cation cannot be relied upon if the SVACK is tied LOW.
DBD-DB7 (BidirectiQnal Data Bus, Input/Output)
These eight bidirectional lines are used to transfer command,
status and operand information between the device and the host
processor. D80 is the least significant and D87 is the most
significant bit position. HIGH on the data bus line corresponds to
1 and lOW corresponds to O.
When pushing operands on the stack using the data bus, the
least significant byte must be pushed first and most significant
byte last. When popping the stack to read the result of an opera-
tion, the most significant byte will be available on the data bus
first and the least significant byte will be the last. Moreover, for
pushing operands and popping results, the number of transac-
tions must be equal to the proper number of bytes appropriate
for the chosen format. Otherwise, the internal byte pointer will
not be aligned properly. The Am9511A single precision format
requires 2 bytes, double precision and floating-point formats re-
quire 4 bytes.
CS (Chip Select, Input)
This input must be LOWto accomplish any read or write opera-
tion to the Am9511A.
To perform a write operation data is presented on D80 through
D87 lines, C/O is driven to an appropriate level and the CS input
is made lOW. However, actual writing into the Am9511 A cannot
start until WR is made LOW. After initiating the write operation
by a WR HIGH to lOW transition, the PAUSE output will go
LOW momentarily (TPPWW).
The WR input can go HIGH after PAUSE goes HIGH. The data
lines, cio input and the CS input can change when appropriate
hold time requirements are satisfied. See write timing diagram
To perform a read operation an appropriate logic level is estab-
lished on the cio input and CS is made LOW. The Read opera-
tion does not start until the RD input goes LOW. PAUSE will go
LOW for a period of TPPWR. When PAUSE goes back HIGH
again, it indicates that read operation is complete and the re-
quired information is available on the DBO through D87 lines.
This information will remain on the data lines as long as RD input
is lOW. The RD input can return HIGH anytime after PAUSE
goes HIGH. The CS input and cin inputs can change anytime
after RD returns HIGH. See read timing diagram for details.
RD (Read, Input)
A LOW on this input is used to read information from an internal
location and gate that information on to the data bus. The CS
cininput must be LOW to accomplish the read operation. The
clo,input determines what internal location is of interest. See
CS input descriptions and read timing diagram for details. If the
END output was LOW, performing any read operation will make
the END output go HIGH after the HIGH to LOW transition of the
RD input (assuming CS is LOW).