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AMCC
AMCC

S3051 Datasheet Preview

S3051 Datasheet

2.5 GBPS LIMITING AMPLIFIER

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S3051 pdf
DEVICE
S2P.E5CGIFBICPASTILOINMITING AMPLIFIER
2.5 GBPS LIMITING AMPLIFIER
FEATURES
• 2 GHz Bandwidth
• 32dB Gain
• Single +5V Power Supply
• Fully Differential Architecture
• 16 pin Glass-Metal Package
APPLICATIONS
• SONET OC-48
• Fiber Optic Data Links
• High-Speed FM Limiting Amplifier
®
S3051
S3051
GENERAL DESCRIPTION
The S3051 limiting amplifier with its high gain and wide
bandwidth is ideal for use as a post amplifier in fiber
optic receivers with data rates up to 2.5 Gbps. The
amplifier's gain is 32dB, and differential signals as
small as 12 mVp-p, can be amplified to 900 mVp-p.
Figure 1 shows a typical system application.
Figure 1. System Block Diagram
VCC
OUT+
CBYP
CIN
INPUT
OUT–
CIN
CBYP
V+REF
DIN+
DOUT+
S3051
DIN-
DOUT–
V–REF
July 14, 1999 / Revision B
1



AMCC
AMCC

S3051 Datasheet Preview

S3051 Datasheet

2.5 GBPS LIMITING AMPLIFIER

No Preview Available !

S3051 pdf
S3051
DETAILED DESCRIPTION
The S3051 is an integrated limiting amplifier in-
tended for high-frequency fiber-optic applications.
The circuit connects to typical transimpedance am-
plifiers found within a fiber-optic link. The linear
signal output from a transimpedance amplifier can
contain significant amounts of noise, and may vary
in amplitude over time. The S3051 limiting amplifier
quantizes the signal, and outputs a voltage limited
waveform over a 38 dB input dynamic range.
At low signal levels, below 12 mVp-p, the circuit be-
haves as a linear amplifier. At higher levels the
device becomes a limiting amplifier.
2.5 GBPS LIMITING AMPLIFIER
The referred wideband input noise (160 µVrms) al-
lows for a less than 1E-9 Bit Error Rate for inputs
down to 2 mVp-p.
The S3051 is designed to allow adjustment of the
DC offset between the DIN+ and DIN– inputs. V+REF
can be used as a reference from which the required
offset can be subtracted to set the DC bias level at
DIN–. Similarly, V–REF can be used to set the DC
bias level at DIN+. (See Application Information).
If no adjustment is made to the input DC bias level,
two resistors can be connected in a negative feed-
back configuration in order to cancel any DC offset
at the input. This will minimize the pulse width distor-
tion. (See separate S3051 Limiting Amplifier
Application document.)
Figure 2. Functional Block Diagram
NC
110pF
8
V–REF 9
DIN– 10
11
DIN+
505k
5k
GS1
VCC(OB)
7
GND(OB)
GND(OB)
65
4
GS2
3
OB
2
12
V+REF
50
110pF
5k
5k
1
GND(OB)
DOUT–
DOUT+
GND(OB)
VCC= +5V
NC ..... No Connect
13 14 15 16
VCC(GS1,GS2) VCC(GS1,SS2) GND(GS1,GS2) GND(GS1,GS2)
2 July 14, 1999 / Revision B


Part Number S3051
Description 2.5 GBPS LIMITING AMPLIFIER
Maker AMCC
Total Page 14 Pages
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