MC95FR464 Datasheet | ABOV

MC95FR332/432/364/464 ABOV SEMICONDUCTOR Co., Ltd. 8-BIT MICROCONTROLLERS MC95FR332/432 MC95FR364/464 Data Sheet (Rev.2.0) January, 2012 Rev.2.0 MC95FR332/432/364/464 REVISION HISTORY VERSION 0.0 (June 28, 2008) Initial Version VERSION 0.1 (November 27, 2008) 1. Change OCD Ports from P1[1:0] to P2[2:1]. 2. Change address of RMR(Remocon Mode Register) from BAH to E8H. 3. Fix the sequence of generating reset signal due to BOD when the device enters STOP mode and wakes up by an interrupt. 4. Append input capture function of timer 2, input capture function and pwm output function of timer 3. VERSION 0.1 (November 27, 2008) 1. Correct the method of controlling REMOUT port. VERSION 0.3 (April 27, 2009) 1. Fix BODOUT0/1/2/3/4 level. BODOUT0 : 1.70V (Typ.) ± 50m V BODOUT1/2/3/4 : 1.85, 1.95, 2.05, 2.15 (Typ.) ± 100m V VERSION 0.4 (May 25, 2009) 1. Correct operating mode description. 2. Fix BODOUT1/2/3/4 level BODOUT1/2/3/4 : 1.75, 1.85, 1.95, 2.05 (Typ.) ± 100m V VERSION 0.5 (July 29, 2009) 1. 1.2 Features : Endurance 10,000 times 2. 6. PORT STRUCTURE : Figure 6.1 & 6.2 3. BODOUT0 level : 1.65 ± 100m V 4. 7.6 DC CHARACTERISTICS 5. 10.6 Effective time of Interrupt Request : Figure 10.4 6. 10.7 Multiple Interrupts : Figure 10.5 7. 12.2 PERIPHERAL OPERATION IN SLEEP/STOP/BOD MODE : Table 12-1 8. Figure 12.2 Entry into BOD mode and Release sequence 9. 13.4 Noise Canceller for External Reset Pin : fix TRNC (2us  8us) 10. Figure 13.5 & 13.10 : Fix config read time and reset release time 11. 15.5.3 : Fix function “void eeprom_init(unsigned int addr)” 12. 16.1 FUSE Control Register VERSION 0.6 (September 15, 2009) 1. 1.2 Features : remove WT January, 2012 Rev.2.0 MC95FR332/432/364/464 2. 12.0 POWER MANAGEMENT : Correct timing diagram in Figure 12.2~12.4. 3. Table 15-5 Memory protection using lock bit 4. Fix BODOUT0 in Table 7-4 : 1.60V~1.75V VERSION 0.7 (November 5, 2009) 1. Fix POL0 to POL1 in Figure 11-14 & 11-15. 2. Fix POL0 to POL3 in Figure 11-18 through Figure...