| Description | The CTS100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual gate design of the CTS100ELT22 makes it ideal for applications that require the translation of a clock and a data signal. The CTS100ELT22 is a direct replacement for the ON Semi MC100ELT22, MC100LVELT22... |
| Features |
0.5ns Typical Propogation Delay <100ps Typical Output to Output Skew Flow Through Pinouts Differential PECL Output RoHS Compliant Pb Free Packages BLOCK DIAGRAM DESCRIPTION The CTS100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline ... |
| Datasheet |
 CTS100ELT22 Datasheet - 212.42KB |
