| Part Number | PLL102-108 |
| Manufacturer | PhaseLink Corporation |
| Title | Programmable DDR Zero Delay Clock Driver |
| Description | The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clo... |
| Features |
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of ten differential outputs. • Track spread spectrum clocking for EMI reduction. • Programmable delay between CLK_INT and ... |
| Datasheet |
 PLL102-108 Datasheet
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