| Part Number | DM74S112 |
| Manufacturer | Fairchild Semiconductor |
| Title | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| Description | This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-... |
| Features |
n-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Inputs
Outputs
PR CLR CLK J K
Q
Q
L H X XX H
L
HL
X XX L
H
LL
X X X H*
H*
HH HH HH HH
↓
LL
Q0
↓ HL H
Q0 L
↓ LH L
H
↓ HH
Toggle
HH
H X X Q0
Q...
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| Datasheet |
 DM74S112 Datasheet
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