| Part Number | 54SXxx |
| Manufacturer | Actel |
| Title | General Purpose SDRAM Controller |
| Description | This is the system clock. The controller can transfer data at this rate during bursts. This is a reset signal. Assertion of this signal causes th... |
| Features |
g the RD_BE_RDY signal. The WR_BE_RDY and RD_BE_RDY signals are one-stage pipelined. On write cycles, the WR_BE_RDY signal is asserted one clock cycle prior to the time when data can actually be accepted by the SDRAM. On read cycles, the RD_BE_RDY si...
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| Datasheet |
 54SXxx Datasheet
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