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Cypress Semiconductor Electronic Components Datasheet



W232

Ten Output Zero Delay Buffer


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W232 pdf
Features
• Well suited to both 100- and 133-MHz designs
• Ten/Eleven LVCMOS/LVTTL outputs
• 3.3V power supply
• Available in 24-pin TSSOP package
W232
Ten Output Zero Delay Buffer
Key Specifications
Operating Voltage: ................................................ 3.3V±10%
Operating Range: ........................25 MHz < fOUT < 140 MHz
Cycle-to-Cycle Jitter: ................................................<150 ps
Output to Output Skew: ............................................<100 ps
Phase Error Jitter: .....................................................<125 ps
Static Phase Error: ....................................................<150 ps
Block Diagram
Pin Configurations
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4
4
4
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4
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4
4
4
4
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AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE0:4
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
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9''
4
4
4
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4
4
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24 CLK
23 AVDD
22 VDD
21 Q8
20 Q7
19 GND
18 GND
17 Q6
16 Q5
15 VDD
14 OE5:8
13 FBIN
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 9''
 4
 4
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 4
 4
 4
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Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 8, 2000, rev. *C



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W232 pdf
W232
Pin Definitions
Pin
Name
Pin No.
(-09)
CLK 24
FBIN
13
Q0:8
FBOUT
3, 4, 5, 8,
9, 16, 17,
20, 21
12
AVDD
AGND
VDD
GND
OE0:4
OE
OE5:8
23
1
2, 10, 15,
22
6, 7, 18,
19
11
--
14
Pin No.
(-10)
24
13
3, 4, 5, 8,
9, 15, 16,
17, 20, 21
12
23
1
2, 10, 14
22
6, 7, 18,
19
--
11
--
Pin
Type
I
I
O
O
P
G
P
G
I
I
I
Pin Description
Reference Input: Output signals Q0:9 will be synchronized to this signal.
Feedback Input: This input must be fed by one of the outputs (typically
FBOUT) to ensure proper functionality. If the trace between FBIN and FBOUT
is equal in length to the traces between the outputs and the signal destina-
tions, then the signals received at the destinations will be synchronized to the
CLK signal input.
Outputs: The frequency and phase of the signals provided by these pins will
be equal to the reference signal if properly laid out.
Feedback Output: Typically this is connected directly to the FBIN input with
a trace equal in length to the traces between outputs Q0:9 and the destination
points of these output signals.
Analog Power Connection: Connect to 3.3V. Use ferrite beads to help re-
duce noise for optimal jitter performance.
Analog Ground Connection: Connect to common system ground plane.
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce
noise for optimal jitter performance.
Ground Connections: Connect to common system ground plane.
Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When
brought to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.
Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When
brought to GND (LOW, 0) outputs Q0:9 are disabled to a LOW state.
Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. When
brought to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.
Overview
The W232 is a PLL-based clock driver designed for use in
systems requiring a large number of synchronous timing sig-
nals. The clock driver has output frequencies of up to 140 MHz
and output-to-output skews of less than 100 ps. The W232
provides minimum cycle-to-cycle and long-term jitter, which is
of significant importance to meet the tight input-to-input skew
budget in DIMM applications.
The W232 was specifically designed to accept SSFTG signals
currently being used in motherboard designs to reduce EMI.
Zero delay buffers which are not designed to pass this feature
through may cause skewing failures.
Output enable pins allow for shutdown of output when they are
not being used. This reduces EMI and power consumption.
2



Part Number W232
Description Ten Output Zero Delay Buffer
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 5 Pages
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