http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf



Cypress Semiconductor Electronic Components Datasheet



W215B

Notebook PC system Frequency Generator



No Preview Available !

W215B pdf
PRELIMINARY
W215B
Notebook PC System Frequency Generator for K6 Processors
Features
• Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, USB plus 14.318 MHz (REF0:1)
• MODE input pin selects optional power management
input control pins (reconfigures pins 26 and 27)
• Two fixed outputs separately selectable as 24-MHz or
48-MHz (default = 48-MHz)
• VDDQ3 = 3.3V±5%, VDDQ2 = 3.3V±5%
• Uses external 14.318-MHz crystal
• Available in 48-pin TSSOP (6.1-mm)
10CPU output impedance
Table 1. Pin Selectable Frequency
95/100_SEL
CPU, SDRAM
Clocks (MHz)
0 95.0
1 100.0
PCI Clocks
CPU/3
CPU/3
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
www.DataSheet4U.com
CPU_2.5#
MODE
I/O
Control
Stop
Output
Control
95/100_SEL
PLL 1
PWR_DWN#
Stop
Output
Control
Power
Down
Control
PLL2
VDDQ3
REF0
REF1
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
CPU2
CPU3
VDDQ3
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
Pin Configuration
REF1
REF0
GND
X1
X2
MODE
VDDQ3
PCI_F
PCI0
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
GND
95/100_SEL
Reserved
Reserved
VDDQ3
48/24MHZ
48/24MHZ
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SDRAM5
SDRAM6/CPUSTOP#
SDRAM7/PCISTOP#
PCI_F
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
48/24MHZ
48/24MHZ
48 VDDQ3
47 CPU_2.5#
46 VDDQ2
45 IOAPIC
44 PWR_DWN#
43 GND
42 CPU0
41 CPU1
40 VDDQ2
39 CPU2
38 CPU3
37 GND
36 SDRAM0
35 SDRAM1
34 VDDQ3
33 SDRAM2
32 SDRAM3
31 GND
30 SDRAM4
29 SDRAM5
28 VDDQ3
27 SDRAM6/CPU_STOP#
26 SDRAM7/PCI_STOP#
25 VDDQ3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07222 Rev. *A*
Revised December 15, 2002



No Preview Available !

W215B pdf
PRELIMINARY
W215B
Pin Definitions
Pin Name
Pin
No.
CPU0:3
42, 41, 39,
38
PCI0:5
9, 11, 12, 13,
14, 16
PCI_F
8
SDRAM0:5
36, 35, 33,
32, 30, 29
SDRAM6/
CPU_STOP#
27
SDRAM7/
PCI_STOP#
www.DataSheet4U.com
26
IOAPIC
48/24MHz
45
22, 23
REF0:1
CPU_2.5#
95/100_SEL
X1
X2
2, 1
47
18
4
5
Pin
Type
O
O
O
O
I/O
I/O
O
O
O
I
I
I
I
Pin Description
CPU Outputs 0 through 3: These four CPU outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2.
PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run synchro-
nous to the CPU clock outputs. Output voltage swing is controlled by voltage applied
to VDDQ3.
SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has dual
functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the
CPU_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 6.
Regarding use as a CPU_STOP# input: When brought LOW, clock outputs CPU0:3
are stopped LOW after completing a full clock cycle (23 CPU clock latency). When
brought HIGH, clock outputs CPU0:3 are started beginning with a full clock cycle (23
CPU clock latency).
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has dual
functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the
PCI_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 7.
PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW after
completing a full clock cycle. When brought HIGH, clock outputs PCI0:5 are started
beginning with a full clock cycle. Clock latency provides one PCI_F rising edge of PCI
clock following PCI_STOP# state change.
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following device
power-up. Either or both can be changed to 24 MHz through use of the serial data
interface (Byte 0, bits 2 and 3). Output voltage swing is controlled by voltage applied
to VDDQ3
Fixed 14.318-MHz Outputs 0 through 1: Used for various system applications. Out-
put voltage swing is controlled by voltage applied to VDDQ3. REF0 is stronger than
REF1 and should be used for driving ISA slots.
Set to logic 1 for 3.3V CPU I/O.
95- or 100-MHz Input Selection: Selects power-up default CPU clock frequency as
shown in Table 1 on page 1 (also determines SDRAM and PCI clock frequency selec-
tions).
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
Document #: 38-07222 Rev. *A*
Page 2 of 14



Part Number W215B
Description Notebook PC system Frequency Generator
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 14 Pages
PDF Download
W215B pdf
Download PDF File
W215B pdf
View for Mobile




Featured Datasheets

Part Number Description Manufacturers PDF
W210 Spread Spectrum FTG for VIA K7 Chipset W210
Cypress Semiconductor
PDF
W210TS HIGH VOLTAGE PHOTO MOS RELAY W210TS
ETC
PDF
W215 Vitreous Enamelled Wirewound Resistors W215
ETC
PDF
W2152 A Major Advance W2152
ETC
PDF
W215B Notebook PC system Frequency Generator W215B
Cypress Semiconductor
PDF
W216 Spread Spectrum FTG for 440BX and VIA Apollo Pro-133 W216
Cypress Semiconductor
PDF


Part Number Start With

0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z

site map

webmaste! click here

contact us

Buy Components