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Cypress Semiconductor Electronic Components Datasheet



W195B

Frequency Generator for Integrated Core Logic


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W195B pdf
PRELIMINARY
W195B
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clocks
• Nine copies of SDRAM clocks
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Two copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
• Power-down control
• I2C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: .................................................. 500 ps
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48MHz Output Skew: ........................ 250 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@100 MHz): ..................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: ....................................................± 0.5 ns
Table 1. Frequency Selections
FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC
1 1 1 1 133.6 133.6 66.8 33.4 16.7
1110
Reserved
1 1 0 1 100.2 100.2 66.8 33.4 16.7
1 1 0 0 66.8 100.2 66.8 33.4 16.7
1 0 1 1 105 105 70 35 17.5
1 0 1 0 110 110 73.3 36.7 18.3
1 0 0 1 114 114 76 38 19
1 0 0 0 119 119 79.3 39.7 19.8
0 1 1 1 124 124 82.7 41.3 20.7
0 1 1 0 129 129 64.5 32.3 16.1
0 1 0 1 95
95 63.3 31.7 15.8
0 1 0 0 138 138 69 34.5 17.3
0 0 1 1 150 150 75 37.5 18.8
0 0 1 0 75 113 75 37.5 18.8
0 0 0 1 90 90 60 30 15
0 0 0 0 83.3 125 83.3 41.7 20.8
Block Diagram
X1 XTAL
X2 OSC
PLL REF FREQ
SDATA
SCLK
FS3*
FS2*
FS1*
FS0*
I2C
Logic
Divider,
Delay,
and
Phase
Control
Logic
PLL 1
PWRDWN#
PLL2
/2
VDDQ3
REF2X/FS3*
VDDQ2
CPU0:1
2
APIC
VDDQ3
3V66_0:1
2
PCI0/FS0*
PCI1/FS1*
PCI2/FS2*
PCI3:7
5
SDRAM0:8
9
VDDQ3
48MHz_0:1
2
SI0/24_48#MHz*
[1]
Pin Configuration
REF2x/FS3*
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
GND
FS0*/PCI0
FS1^/PCI1
FS2*/PCI2
GND
PCI3
PCI4
VDDQ3
PCI5
PCI6
PCI7
GND
48MHz_0
48MHz_1
SI0/24_48#MHz*
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ2
47 APIC
46 VDDQ2
45 CPU0
44 CPU1
43 GND
42 VDDQ3
41 SDRAM0
40 SDRAM1
39 SDRAM2
38 GND
37 SDRAM3
36 SDRAM4
35 SDRAM5
34 VDDQ3
33 SDRAM6
32 SDRAM7
31 SDRAM8
30 GND
29 PWRDWN#*
28 SCLK
27 VDDQ3
26 GND
25 SDATA
Note:
1. Internal 250K pull-up or pull down resistors present on inputs
marked with * or ^ respectively. Design should not rely solely on
internal pull-up or pull down resistor to set I/O pins HIGH or LOW
respectively.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **



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W195B pdf
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W195B
Pin Definitions
Pin Name
REF2x/FS3
Pin No.
1
X1
X2
PCI0/FS0
3
4
10
PCI1/FS1
11
PCI2/FS2
12
PCI3:7
3V66_0:1
14, 15, 17, 18,
19
7,8
48MHz_0:1
SIO/
24_48#MHz
21, 22
23
PWRDWN#
29
CPU0:1
45, 44
SDRAM0:8,
APIC
41, 40, 39, 37,
36, 35, 33, 32,
31
47
SDATA
SCLK
VDDQ3
VDDQ2
25
28
2, 6, 16, 24, 27,
34, 42
46, 48
GND
5, 9, 13, 20, 26,
30, 38, 43
Pin
Type
I/O
I
I
I/O
I/O
I/O
O
O
O
I/O
I
O
O
Pin Description
Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock out-
put. This pin also serves as the select strap to determine device operating frequency
as described in Table 1.
Crystal Input: This pin has dual functions. It can be used as an external 14.318-
MHz crystal connection or as an external reference frequency input.
Crystal Output: An input connection for an external 14.318-MHz crystal connec-
tion. If using an external reference, this pin must be left unconnected.
PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin
doubles as the select strap to determine device operating frequency as described
in Table 1.
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually
turned off via I2C interface.
66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled
by FS0:3 (see Table 1).
48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.
Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.
During power-up, it also serves as a selection strap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.
Power Down Control: LVTTL-compatible input that places the device in power-
down mode when held LOW.
CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies
depending on the configuration of FS0:3. Voltage swing is set by VDDQ2.
SDRAM Clock Outputs: 3.3V outputs for SDRAM. The operating frequency is
controlled by FS0:3 (see Table 1).
O Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs. Voltage swing set by VDDQ2.
I/O Data pin for I2C circuitry.
I Clock pin for I2C circuitry.
P 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buff-
ers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V.
P 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
G Ground Connections: Connect all ground pins to the common system ground
plane.
2



Part Number W195B
Description Frequency Generator for Integrated Core Logic
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 13 Pages
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