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Cypress Semiconductor Electronic Components Datasheet



W167B

133-MHz Spread Spectrum FTG for Pentium II Platforms



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W167B pdf
PRELIMINARY
W167B
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Three copies of CPU outputs selectable frequency
• Three copies of 3V66 selectable frequency output at
3.3V
• Ten copies of PCI clocks (selectable frequency), 3.3V
• One double strength 14.318-MHz reference output at
3.3V
• One copy of 48-MHz USB clock
• One copy of selectable 24-/48-MHz for SIO
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Three copies of IOAPIC
• Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... VDDQ2 = 2.5V±5%
VDDQ3 = 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew: ...................................... 175 ps
IOAPIC, 3V66 Output Skew: ....................................... 250 ps
PCI0:8 Pin to Pin Skew: .............................................. 500 ps
Block Diagram
X1 XTAL
X2 OSC
VDDQ3
REF2X
VDDQ2
CPU_[0:2]
3
SEL133/100#
PLL 1
÷2
÷2/÷1.5
PWRDWN#
Power
Down
Logic
÷2
÷2
SDATA
SCLK
PLL2
Serial
Logic
÷2
CPUdiv2
VDDQ3
3V66_[0:2]
3
PCI0/SEL2*
PCI1/SEL1*
PCI_[2:9]
8
VDDQ2
IOAPIC[0:2]
3
QVD# DQ3
48MHz/SEL0*
SIO/24_48#MHz
Duty Cycle: ................................................................ 45/55%
Spread Spectrum Modulation:................................... ±0.25%
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency
SEL133/
CPU 3V66 PCI IOAPIC
100# SEL2 SEL1 SEL0 MHz MHz MHz MHz
1 1 1 1 133.3 66.7 33.3 16.7
1 1 1 0 138 69 34.5 17.3
1 1 0 1 143 71.5 35.8 17.9
1 1 0 0 148 74 37 18.5
1 0 1 1 150 75 37.5 18.8
1 0 1 0 152.5 76.3 38.1 19.1
1 0 0 1 155 77.5 38.8 19.4
1 0 0 0 160 80 40 20
0 1 1 1 100.2 66.8 33.4 16.7
0 1 1 0 105 70 35 17.5
0 1 0 1 114 76 38 19
0 1 0 0 120 80 40 20
0 0 1 1 66.8 66.8 33.4 16.7
0 0 1 0 124 82.7 41.3 20.7
0 0 0 1 128.5 64.3 32.1 16.1
0 0 0 0 133.9 67 33.5 16.7
Pin Configuration[1]
IOAPIC2
REF2X
VDDQ3
X1
X2
GND
SEL2*/PCI0
SEL1*/PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 VDDQ2
46 IOAPIC0
45 IOAPIC1
44 GND
43 VDDQ2
42 CPUdiv2
41 GND
40 VDDQ2
39 CPU2
38 GND
37 VDDQ2
36 CPU1
35 CPU0
34 SDATA
33 VDDQ3
32 GND
31 PWRDN#*
30 SCLK
29 VDDQ3
28 SIO/24_48#MHz*
27 48MHz/SEL0*
26 GND
25 SEL133/100#
Note:
1. Internal 250-kpull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999



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Pin Definitions
Pin Name
CPU0:2
Pin
No.
35, 36, 39
SEL133/100#
PCI0/SEL2
25
7
PCI1/SEL1
8
PCI2:9
3V66_0:2
CPUdiv2
10, 11, 12,
13, 15, 16,
18, 19
21, 22, 23
42
IOAPIC0:2
48MHZ/SEL0
46, 45, 1
27
SIO/24_48#MHz
28
REF2X
PWRDWN#
X1
X2
SDATA
SCLK
VDDQ2
VDDQ3
GND
2
31
4
5
34
30
37, 40, 43, 47
3, 9, 17, 24,
29, 33
6, 14, 20, 26,
32, 38, 41,
44, 48
Pin
Type
O
I
I/O
I/O
O
O
O
O
I/O
I/O
O
I
I
I
I/O
I
P
P
G
Pin Description
CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage
swing is controlled by voltage applied to VDDQ2.
SEL133/100#: Frequency selection input pin as shown in Table 1.
PCI Clock Output 0 and Selection Bit 2: As an output, this pin works in
conjunction with PCI2:9. When an input, this pin functions as part of the fre-
quency selection address (see Table 1).
PCI Clock Output 1 and Selection Bit 1: As an output, this pin works in
conjunction with PCI2:9. When an input, this pin functions as part of the fre-
quency selection address (see Table 1).
PCI Clock Outputs 2 through 9: Output voltage swing is controlled by voltage
applied to VDDQ3.
66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by
voltage applied to VDDQ3.
CPU-Divide-By-2 Output: This serves as a reference input signal for Direct
Rambus Clock Generator (Cypress W134). The output voltage is determined
by VDDQ2.
I/O APIC Clock Output 0 through 2: Provide outputs synchronous to CPU
clock. See Table 1 and Table 5 for their relation to other system clock outputs.
48-MHz Output and Selection Bit 0: Fixed clock output that defaults to
48-MHz following device power-up. When an input, this pin functions as part of
the frequency selection address (see Table 1).
Super I/O Reference Clock Output and SIO Clock Frequency Select: Fixed
clock output that provides the reference input clock to a Super I/O device. The
output frequency is determined by the input value on this pin during power up.
If input is sampled HIGH, the output operates at 24 MHz, otherwise, the output
operates at 48 MHz.
Fixed 14.318-MHz Output: With double strength driving capability.
Power Down Control
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
Power Connection: Connected to 2.5V power supply.
Power Connection: Connected to 3.3V supply.
Ground Connection: Connect all ground pins to the common system ground
plane.
2



Part Number W167B
Description 133-MHz Spread Spectrum FTG for Pentium II Platforms
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 18 Pages
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