5, 6, 7, 8, 10,
9, 12, 20, 26
3, 15, 19, 28
CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by
SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2.
PCI Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run
synchronously to the CPU clock. Voltage swing is set by the power connection to
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24-MHz or 48-MHz Output: Frequency is set by the state of pin 27 on power-up.
I/O Dual-Function REF2X and SEL48# pin: Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD, pin
14 will output 24 MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
Frequency Selection Input: Selects CPU clock frequency as shown in Table 1 on
I2C Data Pin: Data should be presented to this input as described in the I2C section
of this data sheet. Internal 250-kΩ pull-up resistor.
I2C Clock Pin: The I2C data clock should be presented to this input as described in
the I2C section of this data sheet.
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection: Power supply for core logic and PLL circuitry, PCI, 48-/24-MHz,
and Reference output buffers. Connect to 3.3V supply.
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to
Ground Connections: Connect all ground pins to the common system ground
I/O Pin Operation
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with input
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
Upon W164 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the Reference clock
output buffer is three-stated, allowing the output strapping re-
sistor on the l/O pin to pull the pin and its associated capacitive
clock load to either a logic HIGH or LOW state. At the end of
the 2-ms period, the established logic “0” or “1” condition of the
l/O pin is then latched. Next the output buffer is enabled which
converts the l/O pin into an operating clock output. The 2-ms
timer is started when VDD reaches 2.0V. The input bit can only
be reset by turning VDD off and then back on again.
It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
clock output is 25Ω (nominal) which is minimally affected by
the 10-kΩ strap to ground or VDD. As with the series termina-
tion resistor, the output strapping resistor should be placed as
close to the l/O pin as possible in order to keep the intercon-
necting trace short. The trace from the resistor to ground or
VDD should be kept less than two inches in length to prevent
system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input pe-
riod, a 14.318-MHz output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.