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Cypress Semiconductor Electronic Components Datasheet



W161

133-MHz Spread Spectrum FTG for Pentium II Platforms



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W161 pdf
PRELIMINARY
W161
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• Three copies of CPU outputs at 100 or 133 MHz
• Three copies of 66-MHz output at 3.3V
• Ten copies of PCI clocks at 33 MHz, 3.3V
• Two copies of 14.318-MHz reference output at 3.3V
• One copy of 48-MHz USB clock
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... VDDQ2 = 2.5V±5%
VDDQ3 = 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew: ...................................... 175 ps
IOAPIC, 3V66 Output Skew: ....................................... 250 ps
PCI0:9 Output Skew: .................................................. 500 ps
Duty Cycle: ................................................................... 45/55
Block Diagram
X1 XTAL
X2 OSC
2
REF_[0:1]
3
CPU_[0:2]
SPREAD#
SEL0
SEL1
SEL133/100#
PLL 1
÷2
÷2/÷1.5
CPUdiv2
3
3V66_[0:2]
PWRDWN#
÷2
Power
Down
Logic
÷2
Three-state
Logic
9
PCI_[0:9]
IOAPIC
Spread Spectrum Modulation:..................................... –0.5%
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency
SEL133/100# SEL1 SEL0
Function
0 0 0 All outputs Three-State
0 0 1 (Reserved)
0 1 0 Active 100-MHz, 48-MHz
PLL inactive
0 1 1 Active 100-MHz, 48-MHz
PLL active
1 0 0 Test Mode
1 0 1 (Reserved)
1 1 0 Active 133-MHz, 48-MHz
PLL inactive
1 1 1 Active 133-MHz, 48-MHz
PLL active
Pin Configuration[1]
REF0
REF1
VDDQ3
X1
X2
GND
PCI0
PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 VDDQ2
46 IOAPIC
45 GND
44 VDDQ2
43 CPUdiv2
42 GND
41 VDDQ2
40 CPU2
39 GND
38 VDDQ2
37 CPU1
36 CPU0
35 GND
34 VDDQ3
33 GND
32 PWRDWN#*
31 SPREAD#*
30 SEL1*
29 SEL0*
28 VDDQ3
27 48MHz
26 GND
25 SEL133/100#
Note:
1. Internal 250-kpull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
PLL2
48MHz
Pentium is a registered trademark of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **



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W161 pdf
PRELIMINARY
W161
Pin Definitions
Pin Name
CPU0:2
Pin
No.
36, 37, 40
PCI0:9
CPUdiv2
7, 8, 10, 11, 12,
13, 15, 16, 18,
19
43
3V66_0:2
IOAPIC
48 MHz
SPREAD#
21, 22, 23
46
27
31
PWRDWN#
REF0:1
SEL0:1
SEL133/100#
X1
32
1, 2
29, 30
25
4
X2
VDDQ2
VDDQ3
GND
5
38, 41, 44, 47
3, 9, 17, 24, 28,
34
6, 14, 20, 26,
33, 35, 39, 42,
45, 48
Pin
Type
O
O
O
O
O
O
I
I
I
I
I
I
I
P
P
G
Pin Description
CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage
swing is controlled by voltage applied to VDDQ2.
PCI Clock Outputs 0 through 9: Output voltage swing is controlled by voltage
applied to VDDQ3.
CPU-Divide-By-2 Output: This serves as a reference input signal for Direct
Rambus Clock Generator (Cypress W134). The output voltage is determined
by VDDQ2.
66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by
voltage applied to VDDQ3.
I/O APIC Clock Output: Provides an output synchronous to CPU clock. See
Table 1 for their relation to other system clock outputs.
48-MHz Output: Fixed clock output at 48 MHz.
Spread Spectrum Enable: This input enables spread spectrum modulation
on the PLL1 generated frequency outputs of the W161. Modulation range is
0.5%.
Power Down Control
Fixed 14.318-MHz Output 0 and 1: Output voltage swing is controlled by
voltage applied to VDDQ3.
Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting
clock output modes. As shown in Table 1.
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU
output frequency as shown in Table 1.
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
Power Connection: Connected to 2.5V power supply.
Power Connection: Connected to 3.3V power supply.
Ground Connection: Connect all ground pins to the common system ground
plane.
Overview
The W161, a motherboard clock synthesizer, provides 2.5V
CPU clock outputs for advanced CPU and a CPU-divide-by-2
reference frequency for Direct Rambus Clock Generator (such
Cypress W134) interface. Fixed output frequencies are provid-
ed for other system functions.
CPU Frequency Selection
CPU frequency is selected with input pins 25, 29, and 30
(SEL133/100#, SEL0, and SEL1, respectively). Refer to Table
1 for details.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serial terminated clock
lines. The W161 outputs are CMOS-type, which provide
rail-to-rail output swing.
Crystal Oscillator
The W161 requires one input reference clock to synthesize all
output frequencies. The reference clock can be either an ex-
ternally generated clock signal or the clock generated by the
internal crystal oscillator. When using an external clock signal,
pin X1 is used as the clock input and pin X2 is left open.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W161 incor-
porates the necessary feedback resistor and crystal load ca-
pacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 18 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
18 pF should be used. This will typically yield reference fre-
quency accuracies within ±100 ppm.
2



Part Number W161
Description 133-MHz Spread Spectrum FTG for Pentium II Platforms
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 9 Pages
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