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Cypress Semiconductor Electronic Components Datasheet



W137

Bx Notebook System Frequency Synthesizer



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W137 pdf
W137
Bx Notebook System Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Two copies of CPU output
• Six copies of PCI output (Synchronous w/CPU output)
• One 48-MHz output for USB support
• One selectable 24-/48-MHz output
• Two Buffered copies of 14.318-MHz input reference
signal
• Supports 100-MHz or 66-MHz CPU operation
• Power management control input pins
• Available in 28-pin SSOP (209 mils)
• SS function can be disabled
• See W40S11-02 for 2 SDRAM DIMM support
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU0:1 Output to Output Skew: ................................ 175 ps
CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps
Block Diagram
PCI_F, PCI1:5 Output to Output Skew:........................ 500 ps
PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps
CPU to PCI Output Skew: ............... 1.5–4.0 ns (CPU Leads)
Output Duty Cycle: .................................................... 45/55%
PCI_F, PCI Edge Rate: .............................................. >1 V/ns
CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#,
PWR_DWN# all have a 250-kpull-up resistor.
Table 1. Pin Selectable Frequency
SEL100/66# OE
CPU
PCI Spread%
0/1
0
HI-Z
HI-Z Don’t Care
0 1 66.6 MHz 33.3 See Table 2
1 1 100 MHz 33.3 See Table 2
Table 2. Spread Spectrum Feature
SPREAD#
Spread Profile
0 –0.5% (down spread)
1 0% (spread disabled)
Pin Configuration
X1
X2
CPU_STOP#
SPREAD#
SEL0
SEL1
SEL133/100#
PWRDWN#
PCI_STOP#
XTAL
OSC
2
REF0:1
PLL 1
Power
Down
Logic
STOP
Clock
Logic
÷2
÷2/÷1.5
STOP
Clock
Logic
STOP
÷2 Clock
Logic
÷2
4
CPU0:3
2
CPUdiv2_0:1
4
3V66_0:3
1
PCI_F
7
PCI1:7
3
IOAPIC0:2
GND
X1
X2
PCI_F
PCI1
PCI2
GND
VDDQ3
PCI3
PCI4
PCI5
VDDQ3
48MHz
24/48MHz/OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDDQ3
27 REF0/SEL48#
26 REF1/SPREAD#
25 VDDQ2
24 CPU0
23 CPU1
22 GND
21 GND
20 PCI_STOP#
19 VDDQ3
18 CPU_STOP#
17 PWR_DWN#
16 SEL100/66#
15 GND
Three-state
Logic
PLL2
1
48MHz
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 12, 1999, rev. **



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W137
Pin Definitions
Pin Name
CPU0:1
Pin
No.
24, 23
PCI1:5
PCI_F
5, 6, 9, 10,
11
4
CPU_STOP#
18
PCI_STOP#
20
REF0/SEL48#
27
REF1/SPREAD#
26
24/48MHz/OE
14
48MHz
SEL100/66#
X1
X2
PWR_DWN#
13
16
2
3
17
VDDQ3
VDDQ2
GND
8, 12, 19, 28
25
1, 7, 15, 21,
22
Pin
Type
O
O
O
I
I
I/O
I/O
I/O
O
I
I
I
I
P
P
G
Pin Description
CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2. Frequency is selected per Table 1.
PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3. Frequency is selected per Table 1.
Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the
PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage
swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1.
CPU_STOP# Input: When brought LOW, clock outputs CPU0:1 are stopped LOW
after completing a full clock cycle (23 CPU clock latency). When brought HIGH,
clock outputs CPU0:1 start with a full clock cycle (23 CPU clock latency).
PCI_STOP# Input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
I/O Dual-Function REF0 and SEL48# Pin: Upon power-up, the state of SEL48# is
latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor to
GND causes pin 14 to provide a 48-MHz clock. If the pin is strapped to VDD, pin 14
will provide a 24-MHz clock. After 2 ms, the pin becomes a high-drive output that
produces a copy of 14.318 MHz.
I/O Dual-Function REF1 and SPREAD# Pin: Upon power-up, the state of
SPREAD# is latched. The state is set by either a 10K resistor to GND or to VDD. A
10K resistor to GND enables Spread Spectrum function. If the pin is strapped to VDD,
Spread Spectrum is disabled. After 2 ms, the pin becomes a high-drive output that
produces a copy of 14.318 MHz.
I/O Dual-Function 24-MHz or 48-MHz Output and Output Enable Input: Upon
power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to
GND or to VDD. A 10K resistor to GND latches OE LOW, and all outputs are three-
stated. If the pin is strapped to VDD, OE is latched HIGH and all outputs are active.
After 2 ms, the pin becomes an output whose frequency is set by the state of pin 27
on power-up.
48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by
voltage applied to VDDQ3.
Frequency Selection Input: Select power-up default CPU clock frequency as shown
in Table 1.
Crystal Connection or External Reference Frequency Input: This pin can either
be used as a connection to a crystal or to a reference signal.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Down Control: When this input is LOW, device goes into a low-power standby
condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW
after completing a full clock cycle (23 CPU clock cycle latency). When brought
HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
Power Connection: Connected to 3.3V.
Power Connection: Power supply for CPU0:1 output buffers. Connected to 2.5V.
Ground Connection: Connect all ground pins to the common system ground plane.
2



Part Number W137
Description Bx Notebook System Frequency Synthesizer
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 10 Pages
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