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W134M

(W134M/S) Direct Rambus Clock Generator



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W134M pdf
W134M/W134S
Direct Rambus™ Clock Generator
Features
Description
• Differential clock source for Direct Rambus™ memory The Cypress W134M/W134S provides the differential clock
subsystem for up to 800-MHz data transfer rate
signals for a Direct Rambus memory subsystem. It includes
• Provide synchronization flexibility: the Rambus®
Channel can optionally be synchronous to an external
system or processor clock
• Power-managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mmobile applications
• Works with Cypress CY2210, W133, W158, W159, W161,
oand W167 to support Intel® architecture platforms
.c• Low-power CMOS design packaged in a 24-pin QSOP
(150-mil SSOP) package
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
t4UBlock Diagram
eREFCLK
eMULT0:1
PLL
taShPCLKM
.DaSYNCLKN
Phase
Alignment
Output
Logic
CLK
CLKB
Pin Configuration
VDDIR
REFCLK
VDD
GND
GND
PCLKM
SYNCLKN
GND
VDD
VDDIPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12
24 S0
23 S1
22 VDD
21 GND
20 CLK
19 NC
18 CLKB
17 GND
16 VDD
15 MULT0
14 MULT1
13 GND
www .comS0:1
t4USTOPB
Test
Logic
ww.DataSheeCypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
wDocument #: 38-07426 Rev. *C
Revised June 1, 2005



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W134M pdf
W134M/W134S
Pin Definitions
Pin Name
REFCLK
PCLKM
SYNCLKN
STOPB
PWRDNB
MULT 0:1
No.
2
6
7
11
12
15, 14
Type
Description
I Reference Clock Input. Reference clock input, normally supplied by a system frequency
synthesizer (Cypress W133).
I Phase Detector Input. The phase difference between this signal and SYNCLKN is used
to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
I Phase Detector Input. The phase difference between this signal and PCLKM is used to
synchronize the Rambus Channel Clock with the system clock. Both PCLKM and
SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio
Logic is not used, this pin would be connected to Ground.
I Clock Output Enable. When this input is driven to active LOW, it disables the differential
Rambus Channel clocks.
I Active LOW Power-down. When this input is driven to active LOW, it disables the differ-
ential Rambus Channel clocks and places the W134M/W134S in power-down mode.
I PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to
determine the multiply ratio for the PLL for the input REFCLK.
MULT0
0
0
1
1
MULT1
0
1
1
0
W134M
PLL/REFCLK
4.5
6
8
5.333
W134S
PLL/REFCLK
4
6
8
5.333
CLK, CLKB
S0, S1
20, 18
24, 23
O Complementary Output Clock. Differential Rambus Channel clock outputs.
I Mode Control Input. These inputs control the operating mode of the W134M/W134S.
S0 S1 MODE
0 0 Normal
0 1 Output Enable Test
1 0 Bypass
1 1 Test
NC
VDDIR
VDDIPD
VDD
GND
19
1
10
3, 9, 16, 22
4, 5, 8, 13, 17,
21
No Connect
RefV Reference for REFCLK. Voltage reference for input reference clock.
RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB.
P Power Connection. Power supply for core logic and output buffers. Connected to 3.3V
supply.
G Ground Connection. Connect all ground pins to the common system ground plane.
W133
W158
W159
W161
W167
CY2210
Refclk
W134M/W134S
PLL
Phase
Align
D
Busclk
RMC
RAC
MN
4 DLL
Pclk Synclk
Gear
Ratio
Logic
Figure 1. DDLL System Architecture
Document #: 38-07426 Rev. *C
Page 2 of 12



Part Number W134M
Description (W134M/S) Direct Rambus Clock Generator
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 12 Pages
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