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Cypress Semiconductor Electronic Components Datasheet



W130

Spread Spectrum Desktop/Notebook System Clock



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W130 pdf
PRELIMINARY
W130
Spread Spectrum Desktop/Notebook System Clock
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Six copies of CPU Clock
• Eight copies of PCI Clock (synchronous w/CPU clock)
• Two copies of 14.318-MHz IOAPIC Clock
• Two copies of 48-MHz USB Clock
• Three buffered copies of 14.318-MHz reference input
• Input is a 14.318-MHz XTAL or reference signal
• Selectable 100-MHz or 66-MHz CPU Clocks
• Power management control input pins
• Test mode and output three-state capability
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Clock Jitter: ........................................................ 200 ps
CPU0:5 Clock Skew: ...................................................175 ps
PCI_F, PCI1:7 Clock Skew: ......................................... 500 ps
CPU to PCI Clock Skew: .............. 1.5 to 4.0 ns (CPU Leads)
Logic inputs have 250-kpull-up resistors except SEL100/66#.
Table 1. Pin Selectable Frequency
SEL
100/66# SEL1 SEL0 CPU PCI SPREAD#=0
0 0 0 HI-Z HI-Z Don’t Care
0 0 1 66.6 33.3 ±0.9% Center
0 1 0 66.6 33.3 –1% Down
0 1 1 66.6 33.3 –0.5% Down
1 0 0 X1/2 X1/6 Don’t Care
1 0 1 100 33.3 ±0.9% Center
1 1 0 100 33.3 –1% Down
1 1 1 100 33.3 –0.5% Down
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
CPU_STOP#
100/66#_SEL
SEL0
SEL1
SPREAD#
PCI_STOP#
Stop
Clock
Control
PLL 1
÷2/÷3
Stop
Clock
Control
PWR_DWN#
PPowerr
DDoowwnn
CCoonnttrrooll
PLL2
VDDQ3
REF0
REF1
REF2
VDDQ2
APIC0
APIC1
VDDQ2
CPU0
CPU1
CPU2
CPU3
CPU4
CPU5
VDDQ3
PCI_F
PCI1
PCI2
PCI3
VDDQ3
PCI4
PCI5
PCI6
PCI7
VDDQ3
48MHz
48MHz
Pin Configuration
REF0
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
48MHz
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ3
47 REF2
46 VDDQ2
45 APIC0
44 APIC1
43 VDDQ2
42 CPU0
41 CPU1
40 CPU2
39 CPU3
38 GND
37 VDDQ2
36 CPU4
35 CPU5
34 GND
33 VDDQ3
32 GND
31 PCI_STOP#
30 CPU_STOP#
29 PWRDWN#
28 SPREAD#
27 SEL0
26 SEL1
25 SEL100/66#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 27, 1999, rev. **



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W130 pdf
PRELIMINARY
W130
Pin Definitions
Pin Name
Pin
No.
CPU0:5
42, 41, 40,
39, 36, 35
PCI1:7
8, 10, 11, 13,
14, 16, 17
PCI_F
7
CPU_STOP#
30
PCI_STOP#
31
SPREAD#
APIC0:1
48MHz
REF0:2
SEL100/66#
SEL1, SEL0
X1
X2
PWR_DWN#
28
45, 44
22, 23
1, 2, 47
25, 26, 27
4
5
29
VDDQ3
VDDQ2
GND
9, 15, 19, 21,
33, 48
37,43,46
3, 6, 12, 18,
20, 24, 32,
34, 38
Pin
Type
O
O
O
I
I
I
O
O
O
I
I
I
I
P
P
G
Pin Description
CPU Clock Outputs 0 through 5: These six CPU clock outputs are controlled by
the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ2.
PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
CPU_STOP# Input: When brought LOW, clock outputs CPU0:5 are stopped LOW
after completing a full clock cycle (23 CPU clock latency). When brought HIGH,
clock outputs CPU0:5 start beginning with a full clock cycle (23 CPU clock latency).
PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle.
SPREAD# Input: When brought LOW this pin activates Spread Spectrum clocking.
I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output volt-
age swing is controlled by VDDQ2.
48-MHz Outputs: Fixed clock outputs at 48 MHz. Output voltage swing is controlled
by voltage applied to VDDQ3.
Fixed 14.318-MHz Outputs 0 through 2: Used for various system applications.
Output voltage swing is controlled by voltage applied to VDDQ3.
Frequency Selection Input: Selects power-up default CPU clock frequency as
shown in Table 1 on page 1.
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or reference signal.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Down Control: When this input is LOW, device goes into a low-power con-
dition. All outputs are held LOW while in power-down. CPU and PCI clock outputs
are stopped LOW after completing a full clock cycle (23 CPU clock cycle latency).
When brought HIGH, CPU, SDRAM and PCI outputs start with a full clock cycle at
full operating frequency (3 ms maximum latency).
Power Connection: Power supply for core logic, PLL circuitry, PCI output buffers,
reference output buffers, and 48-MHz output buffers. Connected to 3.3V supply.
Power Connection: Power supply for APIC0:1and CPU0:5 output buffers. Con-
nected to 2.5V supply.
Ground Connection: Connect all ground pins to the common system ground
plane.
2



Part Number W130
Description Spread Spectrum Desktop/Notebook System Clock
Maker Cypress Semiconductor - Cypress Semiconductor
Total Page 8 Pages
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