Dual Input Synchronous MOSFET Driver
• Independent PWM Input Control for High-Side
and Low-Side Gate Drive
• Input Logic Level Threshold 3.0V TTL Compatible
• Dual Output MOSFET Drive for Synchronous
• High Peak Output Current: 2A (typical)
• Internal Bootstrap Blocking Device
• +36V BOOT Pin Maximum Rating
• Low Supply Current: 45 µA (typical)
• High Capacitive Load Drive Capability:
- 3300 pF in 10.0 ns (typical)
• Input Voltage Undervoltage Lockout Protection
• Overtemperature Protection
• Space Saving Packages:
- 8-Lead SOIC
- 8-Lead 3x3 DFN
• 3-Phase BLDC Motor Control
• High Efficient Synchronous DC/DC Buck
• High Current Low Output Voltage Synchronous
DC/DC Buck Converters
www.DataShee•t4HUi.gcohmInput Voltage Synchronous DC/DC Buck
• Core Voltage Supplies for Microprocessors
The MCP14700 is a high-speed synchronous
MOSFET driver designed to optimally drive a high-side
and low-side N-Channel MOSFET. The MCP14700
has two PWM inputs to allow independent control of the
external N-Channel MOSFETs. Since there is no
internal cross conduction protection circuitry the
external MOSFET dead time can be tightly controlled
allowing for more efficient systems or unique motor
The transition thresholds for the PWM inputs are
typically 1.6V on a rising PWM input signal and typically
1.2V on a falling PWM input signal. This makes the
MCP14700 ideally suited for controllers that utilize 3.0V
TTL/CMOS logic. The PWM inputs are internally pulled
low ensuring the output drive signals are low if the
inputs are floating.
The HIGHDR and LOWDR peak source current
capability of the MCP14700 device is typically 2A.
While the HIGHDR can sink 2A peak typically, the
LOWDR can sink 3.5A peak typically. The low
resistance pull-up and pull-down drive allow the
MCP14700 to quickly transition a 3300 pF load in
typically 10 ns. Bootstrapping for the high-side drive is
internally implemented which allows for a reduced
system cost and design complexity.
The MCP14700 features under voltage lock out
(UVLO) with a typical hysteresis of 500 mV.
Overtemperature protection with hysteresis is also
featured on the device.
PWMHI 2 EP 7 BOOT
PWMLO 3 9 6 VCC
* Includes Exposed Thermal Pad (EP); see Table 3-1.
© 2009 Microchip Technology Inc.