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Freescale Semiconductor Electronic Components Datasheet



MC100ES6139

Clock Generation Chip


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Freescale Semiconductor
Technical Data
3.3 V ECL/PECL/HSTL/LVDS ÷2/4,
÷4/5/6 Clock Generation Chip
The MC100ES6139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed
explicitly for low skew clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output edges are all precisely
aligned. The device can be driven by either a differential or single-ended ECL or,
if positive power supplies are used, LVPECL input signals. In addition, by using
the VBB output, a sinusoidal source can be AC coupled into the device. If a single-
ended input is to be used, the VBB output should be connected to the CLK input
and bypassed to ground via a 0.01 µF capacitor.
The common enable (EN) is synchronous so that the internal dividers will only
be enabled/disabled when the internal clock is already in the LOW state. This
avoids any chance of generating a runt clock pulse on the internal clock when the
device is enabled/disabled as can happen with an asynchronous control. The
internal enable flip-flop is clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the negative edge of the clock
input.
Upon startup, the internal flip-flops will attain a random state; therefore, for
systems which utilize multiple ES6139s, the master reset (MR) input must be
asserted to ensure synchronization. For systems which only use one ES6139,
the MR pin need not be exercised as the internal divider design ensures
synchronization between the ÷2/4 and the ÷4/5/6 outputs of a single device. All
VCC and VEE pins must be externally connected to power supply to guarantee
proper operation.
The 100ES Series contains temperature compensation.
Features
• Maximum Frequency >1.0 GHz Typical
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• 50 ps Output-to-Output Skew
• PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V
• ECL Mode Operating Range: VCC = 0 V with VEE = –3.135 V to –3.8 V
• Open Input Default State
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
• VBB Output
• LVDS and HSTL Input Compatible
• 20-Lead Pb-Free Package Available
MC100ES6139
Rev 3, 06/2005
MC100ES6139
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
ORDERING INFORMATION
Device
Package
MC100ES6139DT
TSSOP-20
MC100ES6139DTR2
TSSOP-20
MC100ES6139EJ
TSSOP-20 (Pb-Free)
MC100ES6139EJR2 TSSOP-20 (Pb-Free)
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© Freescale Semiconductor, Inc., 2005. All rights reserved.



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VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE
20 19 18 17 16 15 14 13 12 11
12
VCC EN
3456789
CLK CLK VBB MR VCC
10
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View)
DIVSELa
CLK
CLK
Table 1. Pin Description
Pin
CLK(1), CLK(1)
EN(1)
MR(1)
Function
ECL Diff Clock Inputs
ECL Sync Enable
ECL Master Reset
VBB
Q0, Q1, Q0, Q1
ECL Reference Output
ECL Diff ÷2/4 Outputs
Q2, Q3, Q2, Q3
DIVSELa(1)
DIVSELb0(1)
DIVSELb1(1)
ECL Diff ÷4/5/6 Outputs
ECL Freq. Select Input ÷2/4
ECL Freq. Select Input ÷4/5/6
ECL Freq. Select Input ÷4/5/6
VCC ECL Positive Supply
VEE ECL Negative Supply
1. Pins will default low when left open.
Q0
÷2/4 Q0
R Q1
Q1
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EN
MR
DIVSELb0
DIVSELb1
VEE
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÷4/5/6
R
Figure 2. Logic Diagram
Q2
Q2
Q3
Q3
Table 2. Function Tables
CLK
EN
ZL
ZZ H
XX
X = Don’t Care
Z = Low-to-High Transition
ZZ = High-to-Low Transition
DIVSELa
L
H
DIVSELb0
DIVSELb1
LL
HL
LH
HH
MR Function
L Divide
L Hold Q0:3
H Reset Q0:3
Q0:1 Outputs
Divide by 2
Divide by 4
Q2:3 Outputs
Divide by 4
Divide by 6
Divide by 5
Divide by 5
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MC100ES6139
2
Advanced Clock Drivers Device Data
Freescale Semiconductor



Part Number MC100ES6139
Description Clock Generation Chip
Maker Freescale Semiconductor - Freescale Semiconductor
Total Page 12 Pages
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