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Freescale Semiconductor Electronic Components Datasheet



MC100ES6056

2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer


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MC100ES6056 pdf
Freescale Semiconductor
Technical Data
2.5 V/3.3 V ECL/PECL/LVDS
Dual Differential 2:1 Multiplexer
The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential
data path makes the device ideal for multiplexing low skew clock or other skew
sensitive signals. Multiple VBB pins are provided.
The VBB pin, an internally generated voltage supply, is available to this device
only. For single-ended input conditions, the unused differential input is connected
to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs.
When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current
sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The device features both individual and common select inputs to address both
data path and random logic applications.
The 100ES Series contains temperature compensation.
Features
• 360 ps Typical Propagation Delays
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
• ECL Mode Operating Range: VCC = 0 V with VEE = –2.375 V to –3.8 V
• Open Input Default State
• Separate and Common Select
• Q Output Will Default LOW with Inputs Open or at VEE
• VBB Outputs
• LVDS Input Compatible
• 20-Lead Pb-Free Package Available
MC100ES6056
Rev 4, 06/2005
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MC100ES6056
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
ORDERING INFORMATION
Device
Package
MC100ES6056DT
TSSOP-20
MC100ES6056DTR2
TSSOP-20
MC100ES6056EJ
TSSOP-20 (Pb-Free)
MC100ES6056EJR2 TSSOP-20 (Pb-Free)
VCC Q0
20 19
Q0 SEL0 COM_SEL SEL1 VCC
18 17 16 15 14
Q1
13
Q1 VEE
12 11
10
10
1 2 3 4 5 6 7 8 9 10
D0a D0a VBB0 D0b D0b D1a D1a VBB1 D1b D1b
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
© Freescale Semiconductor, Inc., 2005. All rights reserved.



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MC100ES6056 pdf
Table 1. Pin Description
Pin
D0a* – D1a*
D0a* – D1a*
Function
ECL Input Data a
ECL Input Data a Invert
D0b* – D1b*
D0b* – D1b*
SEL0* – SEL1*
COM_SEL*
VBB0, VBB1
Q0 – Q1
ECL Input Data b
ECL Input Data b Invert
ECL Indiv. Select Input
ECL Common Select Input
Output Reference Voltage
ECL True Outputs
Q0 – Q1
ECL Inverted Outputs
VCC Positive Supply
VEE Negative Supply
* Input function will default LOW when left open.
Table 2. Function Table
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SEL0
SEL1
COM_SEL Q0, Q0
Q1, Q1
XXHa a
LLLbb
LHL b a
HH L a a
HL L a b
Table 3. General Specifications
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Thermal Resistance
(Junction-to-Ambient)
0 LFPM, 20 TSSOP
500 LFPM, 20 TSSOP
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Value
75 k
75 k
> 4 kV
> 400 V
> 2 kV
140°C/W
100°C/W
MC100ES6056
2
Advanced Clock Drivers Device Data
Freescale Semiconductor



Part Number MC100ES6056
Description 2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer
Maker Freescale Semiconductor - Freescale Semiconductor
Total Page 8 Pages
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