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Freescale Semiconductor Electronic Components Datasheet



MC100ES6014

2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver


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MC100ES6014 pdf
Freescale Semiconductor
Technical Data
2.5 V/3.3 V 1:5 Differential
ECL/PECL/HSTL/LVDS Clock Driver
The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock
distribution in mind, accepting two clock sources into an input multiplexer. The
ECL/PECL input signals can be either differential or single-ended (if the VBB
output is used). HSTL and LVDS inputs can be used when the ES6014 is
operating under PECL conditions.
The ES6014 specifically guarantees low output-to-output skew. Optimal
design, layout, and processing minimize skew within a device and from device to
device.
To ensure that the tight skew specification is realized, both sides of any
differential output need to be terminated identically into 50 even if only one
output is being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/disabled in the
LOW state. This avoids a runt clock pulse when the device is enabled/disabled
as can happen with an asynchronous control. The internal flip flop is clocked on
the falling edge of the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
The MC100ES6014, as with most other ECL devices, can be operated from a
positive VCC supply in PECL mode. This allows the ES6014 to be used for high
performance clock distribution in +3.3 V or +2.5 V systems. Single ended CLK
input pin operation is limited to a VCC 3.0 V in PECL mode, or VEE –3.0 V in
ECL mode. Designers can take advantage of the ES6014's performance to
distribute low skew clocks across the backplane or the board.
Features
• 25 ps Within Device Skew
• 400 ps Typical Propagation Delay
• Maximum Frequency > 2 GHz Typical
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
• ECL Mode: VCC = 0 V with VEE = –2.375 V to –3.8 V
• LVDS and HSTL Input Compatible
• Open Input Default State
• 20-Lead Pb-Free Package Available
MC100ES6014
Rev 3, 06/2005
www.DataSheet4U.com
MC100ES6014
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
ORDERING INFORMATION
Device
Package
MC100ES6014DT
TSSOP-20
MC100ES6014DTR2
TSSOP-20
MC100ES6014EJ
TSSOP-20 (Pb-Free)
MC100ES6014EJR2 TSSOP-20 (Pb-Free)
© Freescale Semiconductor, Inc., 2005. All rights reserved.



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MC100ES6014 pdf
VCC EN VCC CLK1 CLK1 VBB CLK0 CLK0 CLK_SEL VEE www.DataSheet4U.com
20 19 18 17 16 15 14 13 12 11
10
D
Q
123456789
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
10
Q4
Table 1. Pin Description
Pin Function
CLK0*, CLK0** ECL/PECL/HSTL CLK Input
CLK1*, CLK1** ECL/PECL/HSTL CLK Input
Q0:4, Q0:4
ECL/PECL Outputs
CLK_SEL*
ECL/PECL Active Clock Select Input
EN* ECL Sync Enable
VBB Reference Voltage Output
VCC Positive Supply
VEE Negative Supply
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
Table 2. Function Table
CLK0
CLK1 CLK_SEL
EN
LXLL
HX L L
XLHL
XHH L
XXXH
* On next negative transition of CLK0 or CLK1
Table 3. General specifications
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Thermal Resistance (Junction-to-Ambient)
0 LFPM, 20 TSSOP
500 LFPM, 20 TSSOP
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Value
75 k
75 k
> 2000 V
> 200 V
> 1500 V
140°C/W
100°C/W
Q
L
H
L
H
L*
MC100ES6014
2
Advanced Clock Drivers Device Data
Freescale Semiconductor



Part Number MC100ES6014
Description 2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
Maker Freescale Semiconductor - Freescale Semiconductor
Total Page 8 Pages
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