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Maxim Integrated Semiconductor Electronic Components Datasheet


MAX11043

Simultaneous Sampling ADCs



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MAX11043 pdf
19-4250; Rev 0; 8/08
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4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
General Description
The MAX11043 features 4 single-ended or differential
channels of simultaneous-sampling ADCs with 16-bit
resolution. The MAX11043 contains a versatile filter
block and programmable-gain amplifier (PGA) per
channel. The filter consists of seven cascaded 2nd-
order filter sections for each channel, allowing the con-
struction of a 14th-order filter. The filter coefficients are
user-programmable. Configure each 2nd-order filter as
lowpass (LP), highpass (HP), or bandpass (BP) with
optional rectification. Gain and phase mismatch of the
analog signal path is better than -50dB.
The ADC can sample up to 800ksps per channel. A
40MHz serial interface provides communication to and
from the device. The SPI™ interface provides through-
put of 1600ksps; 4 channels at 400ksps per channel or
2 channels at 800ksps per channel. A software-selec-
table scan mode allows reading the ADC results while
simultaneously updating the DAC. Other features of the
MAX11043 include an internal (+2.5V) or external
(+2.0V to +2.8V) reference, power-saving modes, and
a PGA with gains of 1 to 64. The PGA includes an
equalizer (EQ) function that automatically boosts low-
amplitude, high-frequency signals for applications such
as CW-chirp radar.
The MAX11043 includes two 8-bit coarse DACs that set
the high and low references for a second-stage 12-bit
fine DAC, typically used for VCO control. Use software
controls to write to the DAC or step the DAC up and
down under hardware control in programmable steps.
The device operates from a +3.0V to +3.6V supply. The
MAX11043 is available in a 40-pin, 6mm x 6mm TQFN
package and operates over the extended -40°C to
+125°C temperature range.
Applications
Automotive Radar Systems
Data Acquisition Systems
Industrial Controls
Power-Grid Monitoring
Features
4 Single-Ended or Differential Channels of
Simultaneous-Sampling, 16-Bit ADCs
±10 LSB INL, ±1 LSB DNL, No Missing Codes
90dB SFDR, -86dB THD, 76dB SINAD,
77dB SNR at 100kHz Input
PGA with Gain of 1, 2, 4, 8, 16, 32, or 64 for
Each Channel
EQ Function Automatically Boosts
High-Frequency, Low-Amplitude Signals
Seven-Stage Internal Programmable Biquad
Filters per Channel
High Throughput, 400ksps per Channel for 4
Channels or 800ksps per Channel for 2 Channels
Dual-Stage DAC
Two 8-Bit Coarse Reference DACs
12-Bit Fine DAC
+2.5V Internal Reference or +2.0V to +2.8V
External Reference
Single +3.3V Operation
Shutdown and Power-Saving Modes
40-Pin, 6mm x 6mm TQFN Package
-40°C to +125°C Operating Temperature
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX11043ATL+ -40°C to +125°C
40 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration
TOP VIEW
30 29 28 27 26 25 24 23 22 21
AINDN 31
20 OSCOUT
AINDP 32
19 OSCIN
AGND 33
18 EOC
REFBP 34
17 I.C.
I.C. 35
AINCN 36
MAX11043
16 SCLK
15 DIN
AINCP 37
14 DOUT
REFC 38
REFB 39
+
*EP 13 CS
12 CONVRUN
AINBP 40
11 DACSTEP
1 2 3 4 5 6 7 8 9 10
SPI is a trademark of Motorola, Inc.
*CONNECT EP TO AGND.
TQFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.



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4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ....................................................-0.3V to +4.0V
DVDD to DGND .....................................................-0.3V to +4.0V
DVREG to DGND...................................................-0.3V to +3.0V
AGND to DGND.....................................................-0.3V to +0.3V
Analog I/O, REFDACH, REFDACL, REFA, REFB, REFC, REFD,
AOUT, REFDAC, REFBP to AGND......-0.3V to (AVDD + 0.3V)
UP/DWN, CONVRUN, SHDN, DACSTEP, EOC, Digital I/O,
OSCIN, OSCOUT to DGND ....................-0.3V to (DVDD + 0.3V)
Maximum Current into Any Pin except AVDD, DVDD, DVREG,
AGND, DGND...............................................................±50mA
Continuous Power Dissipation (TA = +70°C)
TQFN Multilayer Board
(derate 37mW/°C above +70°C) ................................2963mW
TQFN Single-Layer Board
(derate 26.3mW/°C above +70°C) ..........................2105.3mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +3.0V to +3.6V, VDVDD = +3.0V, CDVREG = 10µF, VAGND = VDGND = 0, common-mode input voltage = AVDD/2, VREFBP =
VREFA = VREFB = VREFC = VREFD = +2.5V (external reference), VREFDAC = VREFDACH = +1.25V (external reference), VREFDACL = 0,
CREFBP = CREFA = CREFB = CREFC = CREFD = CREFDAC = 1µF, fSCLK = 38.4MHz, fEXCLK = 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. TA = TMIN to TMAX, unless otherwise noted (Note 1).
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
SIGMA-DELTA ADC
Resolution
N
16
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset-Error Drift
Gain Error
Gain Temperature Coefficient
Channel Gain-Error Matching
INL
DNL Guaranteed monotonic
OE
GE Trimmed with 150Ω/330pF anti-alias filter
Complete analog signal path
-16
-1
-35
-1
-0.25
Channel Offset Matching
Complete analog signal path
-60
DYNAMIC PERFORMANCE (PGA Disabled, PGA Gain = 1 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input
ADC modulator gain = 1
Input-Referred Noise Spectral
Density
100kHz
Second Harmonic to
Fundamental
-80
Third Harmonic to Fundamental
Spurious-Free Dynamic Range
SFDR
-80
77
Channel-to-Channel Isolation
Unused channels are shorted and
unconnected
85
Channel Phase Matching
Between all channels, including complete
analog signal path
TYP
±2
±30
±50
1.2
85
-93
-110
102
108
-0.05
MAX UNITS
+1
+35
+1
+0.25
+60
Bits
LSB
LSB
mV
µV/°C
%
ppm/°C
%
mV
VP-P
nV/Hz
dB
dB
dB
dB
+0.05 Degrees
2 _______________________________________________________________________________________



Part Number MAX11043
Description Simultaneous Sampling ADCs
Maker Maxim Integrated Products - Maxim Integrated Products
Total Page 32 Pages
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