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Elite Semiconductor Memory Technology
Elite Semiconductor Memory Technology


M13S128324A

1M x 32 Bit x 4 Banks Double Data Rate SDRAM



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M13S128324A pdf
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Revision History
Revision 0.1 (May. 13 2005)
-Original
Revision 0.2 (Aug. 08 2005)
-Delete Non-Pb-free of ordering information
-Modify typing error of Pin Arrangement
Revision 1.0 (Mar. 08 2006)
-Delete “Preliminary” at every page
-Modify tWR from 2clk to 15ns
-Modify tWTR from 1clk to 2ns
Revision 1.1 (Oct. 25 2006)
-Add -4BG spec (only for CL4)
Revision 1.2 (Nov. 16 2006)
-Add 100 pin LQFP package
Revision 1.3 (Mar. 02 2007)
-Delete BGA ball name of packing dimensions
Revision 1.4 (Mar. 12 2007)
-Add -3.6 speed grade
Revision 1.5 (Mar. 21 2007)
-Add -4(CL3) specification
Revision 1.6 (Mar. 29 2007)
- Modify A10 to A8 on P26
- Modify the figure on P37
Revision 1.7 (Apr. 17 2007)
- Modify -4(CL3) VDD; VDDQ; spec
Revision 1.8 (May. 2 2007)
- Modify PD spec
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
1/49



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M13S128324A pdf
ESMTwww.DataSheet4U.com
M13S128324A
DDR SDRAM
1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Features
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 2; 2.5; 3;4
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8, full page
z Full page burst length for sequential burst type only
z Start address of the full page burst should be even
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V
z VDD = 2.5V ~ 2.7V, VDDQ = 2.5V ~ 2.7V [for speed -3.6]
z Auto & Self refresh
z 32ms refresh period (4K cycle)
z SSTL-2 I/O interface
z 144Ball FBGA and 100 pin LQFP package
Operating Frequencies :
PRODUCT NO.
MAX FREQ
VDD
PACKAGE COMMENTS
M13S128324A -3.6BG
275MHz
2.6V 144 Ball FBGA Pb-free
M13S128324A -4BG
250MHz
2.5V 144 Ball FBGA Pb-free
M13S128324A -5BG
200MHz
2.5V 144 Ball FBGA Pb-free
M13S128324A -6BG
166MHz
2.5V 144 Ball FBGA Pb-free
M13S128324A -4LG
250MHz
2.5V
100 pin LQFP
Pb-free
M13S128324A -5LG
200MHz
2.5V
100 pin LQFP
Pb-free
M13S128324A -6LG
166MHz
2.5V
100 pin LQFP
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.8
2/49



Part Number M13S128324A
Description 1M x 32 Bit x 4 Banks Double Data Rate SDRAM
Maker Elite Semiconductor Memory Technology - Elite Semiconductor Memory Technology
Total Page 30 Pages
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M13S128324A 1M x 32 Bit x 4 Banks Double Data Rate SDRAM M13S128324A
Elite Semiconductor Memory Technology
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