http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf




Elite Semiconductor Memory Technology
Elite Semiconductor Memory Technology


M13S128168A

2M x 16 Bit x 4 Banks Double Data Rate SDRAM



No Preview Available !

M13S128168A pdf
ESMTwww.DataSheet4U.com
Revision History
Revision 0.1 (15 Jan. 2002)
- Original
Revision 0.2 (19 Nov. 2002)
-changed ordering information & DC/AC characteristics
Revision 0.1
M13S128168A - 5T
M13S128168A - 6T
Revision 0.2
M13S128168A - 6T
M13S128168A - 7.5AB
Revision 0.3 (8 Aug. 2003)
-Change IDD6 from 3mA to 5mA.
Revision 0.4 (27 Aug. 2003)
-Change ordering information & DC / AC characteristics.
Revision 1.0 (21 Oct. 2003)
-Modify tWTR from 2tck to 1tck.
Revision 1.1 (10 Nov. 2003)
-Correct some refresh interval that is not revised.
-Correct some CAS Lantency that is not revised.
Revision 1.2 (12 Jan. 2004)
-Correct IDD1; IDD4R and IDD4W test condition.
-Correct tRCD; tRP unit
-Add tCCD spec.
-Add tDAL spec.
Revision 1.3 (12 Mar. 2004)
-Add Cas Latency=2; 2.5
Revision 1.4 (23 Jun. 2005)
-Add Pb-free to ordering information
-Modify IDD0 and IDD1 spec
-Modify some AC timing unit from tCK to ns.
Revision 1.5 (29 May. 2006)
-Delete CL2 ; CL2.5
-Modify tREFI
-Delete Non-pb-free form ordering information
Revision 1.6 (3 Jan. 2007)
-Add CL2.5
Revision 1.7 (12 Apr. 2007)
-Add BGA package
Revision 1.8 (01 Jun. 2007)
-Delete CL 2.5
Elite Semiconductor Memory Technology Inc.
M13S128168A
Publication Date : Jun. 2007
Revision : 1.8
1/49



No Preview Available !

M13S128168A pdf
ESMTwww.DataSheet4U.com
DDR SDRAM
Features
M13S128168A
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z VDD = 2.375V ~ 2.75V, VDDQ = 2.375V ~ 2.75V
z Auto & Self refresh
z 15.6us refresh interval (64ms refresh period, 4K cycle)
z SSTL-2 I/O interface
z 66pin TSOPII package
Ordering information :
PRODUCT NO.
M13S128168A -5TG
M13S128168A -6TG
M13S128168A -5BG
M13S128168A -6BG
MAX FREQ
200MHz
166MHz
200MHz
166MHz
VDD
2.5V
2.5V
PACKAGE
TSOPII
BGA
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2007
Revision : 1.8
2/49



Part Number M13S128168A
Description 2M x 16 Bit x 4 Banks Double Data Rate SDRAM
Maker Elite Semiconductor Memory Technology - Elite Semiconductor Memory Technology
Total Page 49 Pages
PDF Download
M13S128168A pdf
Download PDF File
M13S128168A pdf
View for Mobile




Featured Datasheets

Part Number Description Manufacturers PDF
M13S128168A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM M13S128168A
Elite Semiconductor Memory Technology
PDF


Part Number Start With

0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z

site map

webmaste! click here

contact us

Buy Components