Data Control Circuit
CS Chip Select
A0 ~ A10
BA0 , BA1
Bank Select Address
Row Address Strobe
Column Address Strobe
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM0-3.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004