Data Control Circuit
A0 ~ A12
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
Bank Select Address
Row Address Strobe
Column Address Strobe
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA12, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2007