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Elite Semiconductor
Elite Semiconductor


M12L128168A

Dynamic RAM



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M12L128168A pdf
ESMT
Revision History
M12L128168A
Revision 0.1 (Augut.30.1999)
- Original
Revision 0.2 (Jun.04.2002)
- Add DC characteristics
- Add -5, -6 speed grade
- Delete –8, -10, -12 speed grade
Revision 1.0 (Oct.31.2002)
- Delete “preliminary”
mRevision 1.1 (Mar.25.2003)
o- Modify DC characteristics
.cRevision 1.2 (Sep.02.2003)
U- Delete -5 speed grace
t4- Speed distribution -6 and -7
eRevision 1.3 (Aug.23.2004)
- M12L128168A -6T 125MHz : CL = 3(P7)
e- Correct polt2 clock suspend during read (P17)
h- Correct polt5 : tRDL(min) = 2clk (P20)
- Correct polt2 read interrupted by precharge
- Modify typing error of P18, P22, P23
taSRevision 1.4 (Oct.31.2002)
- Add Pb-free to ordering information
a- Modify P8 for bank precharge state to idle state
.DRevision 1.5 (Apr.22.2005)
- Modify refresh spec
wwRevision 1.6 (Jun.07.2005)
- Modify tREF spec (15.6μs refresh interval
w- Modify tRFC –7 spec (63ns 70ns)
64ms 4K)
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2005
Revision: 1.7
1/45



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M12L128168A pdf
ESMT
SDRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
M12L128168A
2M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO. MAX FREQ. PACKAGE COMMENTS
M12L128168A-6T 166MHz TSOP II
Pb
M12L128168A-7T 143MHz TSOP II
Pb
M12L128168A-6TG 166MHz TSOP II
Pb-free
M12L128168A-7TG 143MHz TSOP II
Pb-free
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Pin Arrangement
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
A13
A12
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 N C
39 UDQM
38 CLK
37 CKE
36 N C
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2005
Revision: 1.7
2/45



Part Number M12L128168A
Description Dynamic RAM
Maker Elite Semiconductor - Elite Semiconductor
Total Page 30 Pages
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