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Elite Semiconductor
Elite Semiconductor


M11L416256SA

256 K x 16 DRAM EDO PAGE MODE



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EliteMT
DRAM
M11L416256SA
256 K x 16 DRAM
EDO PAGE MODE
FEATURES
X16 organization
EDO (Extended Data-Output) access mode
2 CAS Byte/Word Read/Write operation
Single 3.3V ( ± 10%) power supply
LVTTL-compatible inputs and outputs
512-cycle refresh in 8ms
Refresh modes : RAS only, CAS BEFORE RAS (CBR)
and HIDDEN capabilities
Self-refresh capability
JEDEC standard pinout
Key AC Parameter
tRAC
tCAC
tRC
tPC
-35 35 10 65 14
ORDERING INFORMATION - PACKAGE
40-pin 400mil SOJ
44 / 40-pin 400mil TSOP (Type II)
PRODUCT NO.
PACKING
TYPE
COMMENTS
M11L416256SA-
35 TG
SOJ/TSOPII
Pb-free
M11L416256SA-
35 JP
GENERAL DESCRIPTION
The M11L416256 series is a randomly accessed solid state memory, organized as 262,144 x 16 bits device. It offers
Extended Data-Output , 3.3V( ± 10%) single power supply. Access time (-35) , self-refresh and package type (SOJ, TSOP II)
are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh
capabilities.
Two access modes are supported by this device: Byte access and Word access. Use only one of the two CAS and leave
the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used.
CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH
transiting low will output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 N C
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 N C
29 CASL
28 CASH
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4
1/16



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EliteMT
M11L416256SA
FUNCTIONAL BLOCK DIAGRAM
WE
RAS
CASL
CASH
A0
A1
A2
A3
A4
A5
A6
A7
A8
CONTROL
LOGIC
CLOCK
GENERATOR
COLUMN
9 ADDRESS
BUFFER
REFRESH
CONTROLER
REFRESH
COUNTER
99
ROW.
9 ADDRESS
BUFFERS(9)
DATA-IN BUFFER
IO0
16 :
IO15
COLUMN
9 DECODER
512 16
SENSE AMPLIFIERS
I/O GATING 8
512 x 16
DATA-OUT
BUFFER
16
OE
512 x 512 x 16
512 MEMORY
9 ARRAY
VBB GENERATOR
VCC
VSS
PIN DESCRIPTIONS
PIN NO.
16~19,22~26
14
28
29
13
27
2~5,7~10,31~34,36~39
1,6,20
21,35,40
11,12,15,30
PIN NAME
A0~A8
RAS
CASH
CASL
WE
OE
I/O0 ~ I/O15
VCC
VSS
NC
TYPE
DESCRIPTION
Input
Address Input
Row Address : A0~A8
Column Address : A0~A8
Input
Row Address Strobe
Input
Column Address Strobe / Upper Byte Control
Input
Column Address Strobe / Lower Byte Control
Input
Write Enable
Input
Output Enable
Input / Output Data Input / Output
Supply
Power, 3.3V
Ground
Ground
- No Connect
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4
2/16



Part Number M11L416256SA
Description 256 K x 16 DRAM EDO PAGE MODE
Maker Elite Semiconductor - Elite Semiconductor
Total Page 16 Pages
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