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Integrated Circuit Systems
Integrated Circuit Systems


M1040-11-156.2500

VCSO BASED CLOCK PLL WITH AUTOSWITCH


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M1040-11-156.2500 pdf
Integrated
Circuit
Systems, Inc.
Preliminary Information
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock protection,
frequency translation and jitter
attenuation in OC-12/48 class optical
networking systems. It features dual
differential inputs with two modes of
input selection: manual and
automatic upon clock failure. The clock multiplication
ratios and output divider ratio are pin selectable. This
device provides two outputs. External loop components
allow the tailoring of PLL loop response.
FEATURES
Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz)
Output frequencies of 62.5 to 175 MHz *; Two differen-
tial LVPECL outputs (CML, LVDS options available)
Loss of Lock (LOL) indicator output
Narrow Bandwidth control input (NBW pin);
Initialization (INIT) input overrides NBW at power-up
Dual reference clock inputs support LVDS, LVPECL,
LVCMOS, LVTTL
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure; Hitless
Switching (HS), Phase Build-out (PBO) options enable
SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Industrial temperature available
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
M1040
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
INIT
LOL
3
MR_SEL2:0
MUX
0
1
0
1
Auto
Ref Sel
R Div
LOL
Phase
Detector
M / R Divider
LUT
PLL
Phase
Detector
M Divider
PIN ASSIGNMENT (9 x 9 mm SMT)
MR_SEL1
MR_SEL0
REF_ACK
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 16
31 M 1 0 4 0 15
32 14
33 ( T o p V i e w ) 13
34 12
35 11
36 10
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1040-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
19.44
77.76
155.52
622.08
8 155.52
2 or
1 77.76
0.25
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
Loop Filter
VCSO
P Divider
(1 or 2)
FOUT0
nFOUT0
FOUT1
nFOUT1
P_SEL
Figure 2: Simplified Block Diagram
M1040 Datasheet Rev 0.1
Revised 11Nov2003
M1040 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400



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M1040-11-156.2500 pdf
Integrated
Circuit
Systems, Inc.
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminary Information
PIN DESCRIPTIONS
Number
Name
1, 2, 3, 10, 14, 26 GND
I/O
Ground
Configuration
Description
Power supply ground connections.
4 OP_IN
9 nOP_IN
Input
5
8
nOP_OUT
OP_OUT
Output
6 nVC
7 VC
Input
External loop filter connections. See Figure 5,
External Loop Filter, on pg. 8.
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12 FOUT1
13 nFOUT1
15 FOUT0
16 nFOUT0
17 INIT
Output
Output
Input
No internal terminator
Clock output pair 1. Differential LVPECL.
No internal terminator
Internal pull-UP resistor1
Clock output pair 0. Differential LVPECL.
Power-on Initialization; LVCMOS/LVTTL:
Logic 1 allows device to enter narrow mode if
selected (in addition must have 8 LOL=0 counts)
Logic 0 forced device into wide bandwidth mode.
18 P_SEL
Internal pull-down1
Post-PLL , P divider selection. LVCMOS/LVTTL.
See Table 4, P Divider Selector Values
and Frequencies, on pg. 3.
20 nDIF_REF1
Biased to Vcc/2 2
Reference Differential LVPECL/ LVDS
Input clock input Differential LVPECL/ LVDS, or single
21 DIF_REF1
Internal pull-down resistor1 pair 1.
ended LVCMOS/ LVTTL
22 REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL.
Logic 1 selects DIF_REF1/nDIF_REF1 inputs
Logic 0 selects DIF_REF0/nDIF_REF0 inputs
23 nDIF_REF0
Biased to Vcc/2 3
Reference Differential LVPECL/ LVDS
24
DIF_REF0
Input clock input Differential LVPECL/ LVDS, or single
Internal pull-down resistor1 pair 0.
ended LVCMOS/ LVTTL
25 AUTO
Automatic/manual reselection mode for clock input:
Input
Internal pull-down resistor1
Logic 1 automatic reselection upon clock failure
(non-revertive)
Logic 0 manual selection only (using REF_SEL)
27 MR_SEL2
28 MR_SEL1
29 MR_SEL0
M and R divider value selection. LVCMOS/ LVTTL.
Input Internal pull-UP resistor1 See Table 3, M and R Divider Look-Up Tables (LUT)
on pg. 3.
Reference Acknowledgement pin for input mux state;
30 REF_ACK Output
outputs the currently selected reference input pair:
Logic 1 indicates nDIF_REF1, DIF_REF1
Logic 0 indicates nDIF_REF0, DIF_REF0
31 LOL
Output
Loss of Lock indicator output. 4
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
32 NBW
Narrow Bandwidth enable. LVCMOS/LVTTL:
Input Internal pull-UP resistor1 Logic 1 - Narrow loop bandwidth, RIN = 2100k.
Logic 0 - Wide bandwidth, RIN = 100k.
34, 35, 36
DNC
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 10.
Table 2: Pin Descriptions
Note 2: Biased to Vcc/2, with 50kto Vcc and 50kto ground. Float if using DIF_REF1 as LVCMOS input. See DC Characteristics on pg. 10.
Note 3: Biased to Vcc/2, with 50kto Vcc and 50kto ground. Float if using DIF_REF0 as LVCMOS input. See DC Characteristics on pg. 10.
Note 4: See LVCMOS Outputs in DC Characteristics on pg. 10.
M1040 Datasheet Rev 0.1
2 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. Communications Modules www.icst.com tel (508) 852-5400



Part Number M1040-11-156.2500
Description VCSO BASED CLOCK PLL WITH AUTOSWITCH
Maker Integrated Circuit Systems - Integrated Circuit Systems
Total Page 12 Pages
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