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Clare  Inc.
Clare Inc.


M-986-2R2P

MFC Transceivers


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M-986-2R2P pdf
Features
Direct A-Law PCM digital input
2.048 Mb/s clocking
Programmable forward/backward mode
Programmable compelled/direct control
Operates with standard codecs for analog
interfacing
Microprocessor read/write interface
Binary or 2-of-6 data formats
Single- or dual-channel versions
5 volt power
Applications
Test equipment
Trunk adapters
Paging terminals
Traffic recorders
PBXs
Pin Assignments
Block Diagram
M-986-2R2
MFC Transceivers
Description
The M-986-1R2 and -2R2 MFC Transceivers contain
all the logic necessary to transmit and receive CCITT
R2F (forward) and R2B (backward) multifrequency
signals on one 40-pin integrated circuit (IC). M-986-
1R2 is a single-channel version; M-986-2R2 provides
two channels. R1 single and dual multifrequency
transceivers are also available as M-986-1R1 and -
2R1.
Operating with a 20.48 MHz crystal, the M-986 is
capable of providing a direct digital interface to an A-
law-encoded PCM digital input. Each channel can be
connected to an analog source using a coder-decoder
(codec) as shown in the Block Diagram below.
The M-986 can be configured by the customer to
operate with the transmitter and receiver either cou-
pled together or independently, allowing it to handle a
compelled cycle automatically or via command from
the host processor. For the R2 versions of the M-986,
A-law is used for coding/decoding. The M-986 is con-
figured and controlled through an integral coprocessor
port.
Ordering Information
Part #
M-986-1R2P
M-986-1R2PL
M-986-2R2P
M-986-2R2PL
Description
40-pin plastic DIP, Single Channel
44-pin PLCC, Single Channel
40-pin plastic DIP, Dual Channel
44-pin PLCC, Dual Channel
DS-M976-2R2-R3
www.clare.com
1



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M-986-2R2P pdf
M-986-2R2
Function Description
The M-986 can be set up for various operating modes
by writing two configuration bytes to the coprocessor
port.
Configuration Options
External/Internal Codec Clock (ECLK): If external
codec clocking is selected, an external clocking source
provides an 8kHz transmit framing clock and an 8kHz
receive framing clock. It also provides a serial bit clock
with a frequency that is a multiple of 8 kHz between
2.496 MHz and 216 kHz for exchange of data via the
serial ports. When internal codec clocking is selected,
the M-986 provides an 8kHz framing clock and a 2.048
MHz serial bit clock.
Binary/2 of 6 Input/Output (IOM): When the 2-of-6
input/output is selected, the M-986 encodes the
received R2 MF tone pair into in a 6-bit format, where
each bit represents one of the six possible frequencies.
A logic high level indicates the presence of a frequen-
cy. The digital input to the M-986 that selects the trans-
mitted R2 MF tone pair must also be coded in the
2-of-6 format.
When binary input/output is selected, the M-986
encodes the received R2 MF tone pair into a 4 bit bina-
ry format. The digital input to the M-986 that selects the
transmitted R2 MF tone pair must also be coded in a 4
bit binary format.
Enable/Disable Channel (ENC): When a channel is
disabled, the receiver does not process its codec input
for R2 MF tones, and the transmitter does not respond
to transmit commands. If a transmit command is given
while the channel is enabled, the “tone off” command
must be given before the channel is disabled.
Disabling the channel does not automatically shut off
the transmitter. When a channel is enabled, the receiv-
er and transmitter for that channel function normally.
End-of-Digit Indication (EOD): The end-of-digit indica-
tion option configures the M-986 to inform the host
processor when the far end terminates transmission of
the R2 MF tone it is sending. If this option is disabled,
the host processor will not be notified when tone
transmission terminates.
Automatic Compelled/Manual Sequence Signaling
(CMP): When manual mode is selected, R2 MF tone
transmission is turned on and off only via command
from the host processor.
If the automatic mode is selected, the transmitter and
receiver perform the compelled signaling handshake
automatically. The specifics of operation are different
for the forward and backward configurations.
In forward mode, the transceiver can exist in two
states, STATE 1 and STATE 2:
STATE 1: No backward signal detected.
Transmitter under control of the host.
STATE 2: Backward signal detected.
Transmitter off unconditionally.
Configuration Bytes
Configuration Byte 1
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
0
ECLK
IOM
ENC1
EOD1
CMP1
FB1
0 ECLK
Channels 1 & 2
Channels 1 & 2
Channel 1
Channel 1
Channel 1
Channel 1
Bit 7 Bit 6 Bit 5
IOM
ENC1
EOD1
CMP1
FB1
1 = External codec clock; 0 = Internal codec clock
1 = Binary input/output; 0 = 2-of-6 input/output
1 = Enable channel; 0 = Disable channel
1 = Indicate end of digit; 0 = No end of digit indication
1 = Automatic Compelled mode; 0 = Manual mode
1 = Forward mode (Tx forward frequencies and Rx backward frequencies)
0 = Backward mode (Tx backward frequencies and Rx forward frequencies)
Configuration Byte 2
Bit 4
Bit 3 Bit 2
Bit 1 Bit 0
0
ENC2
EOD2
CMP2
FB2
1
Channel 2
Channel 2
Channel 2
Channel 2
0
0
ENC2
EOD2
CMP2
FB2
1 = Enable channel; 0 = Disable channel
1 = Indicate end of digit; 0 = No end of digit indication
1 = Automatic Compelled mode; 0 = Manual mode
1 = Forward mode (Tx forward frequencies and Rx backward frequencies)
0 = Backward mode(Tx backward frequencies and Rx forward frequencies)
2
www.clare.com
Rev. 3



Part Number M-986-2R2P
Description MFC Transceivers
Maker Clare  Inc. - Clare Inc.
Total Page 13 Pages
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