Logic Block Diagram
There are a Total of 13 inputs and 5 outputs on the ’ACT715/
Data Inputs D0–D7: The Data Input pins connect to the Ad-
dress Register and the Data Input Register.
ADDR/DATA: The ADDR/DATA signal is latched into the de-
vice on the falling edge of the LOAD signal. The signal deter-
mines if an address (0) or data (1) is present on the data bus.
L/HBYTE: The L/HBYTE signal is latched into the device on
the falling edge of the LOAD signal. The signal determines if
data will be read into the 8 LSB’s (0) or the 4 MSB’s (1) of the
Data Registers. A 1 on this pin when an ADDR/DATA is a 0
enables Auto-Load Mode.
LOAD: The LOAD control pin loads data into the Address or
Data Registers on the rising edge. ADDR/DATA and
L/HBYTE data is loaded into the device on the falling edge of
the LOAD. The LOAD pin has been implemented as a
Schmitt trigger input for better noise immunity.
CLOCK: System CLOCK input from which all timing is de-
rived. The clock pin has been implemented as a Schmitt trig-
ger for better noise immunity. The CLOCK and the LOAD
signal are asynchronous and independent. Output state
changes occur on the falling edge of CLOCK.
CLR: The CLEAR pin is an asynchronous input that initial-
izes the device when it is HIGH. Initialization consists of set-
ting all registers to their mask programmed values, and ini-
tializing all counters, comparators and registers. The CLEAR
pin has been implemented as a Schmitt trigger for better
noise immunity. A CLEAR pulse should be asserted by the
user immediately after power-up to ensure proper initializa-
tion of the registers — even if the user plans to (re)program
Note: A CLEAR pulse will disable the CLOCK on the ’ACT715/LM1882 and
will enable the CLOCK on the ’ACT715-R/LM1882-R.
ODD/EVEN: Output that identifies if display is in odd (HIGH)
or even (LOW) field of interlace when device is in interlaced
mode of operation. In noninterlaced mode of operation this
output is always HIGH. Data can be serially scanned out on
this pin during Scan Mode.
VCSYNC: Outputs Vertical or Composite Sync signal based
on value of the Status Register. Equalization and Serration
pulses will (if enabled) be output on the VCSYNC signal in
composite mode only.
VCBLANK: Outputs Vertical or Composite Blanking signal
based on value of the Status Register.
HBLHDR: Outputs Horizontal Blanking signal, Horizontal
Gating signal or Cursor Position based on value of the Sta-
HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating
signal or Vertical Interrupt signal based on value of Status
All of the data registers are 12 bits wide. Width’s of all pulses
are defined by specifying the start count and end count of all
pulses. Horizontal pulses are specified with-respect-to the
number of clock pulses per line and vertical pulses are speci-
fied with-respect-to the number of lines per frame.
REG0 — STATUS REGISTER
The Status Register controls the mode of operation, the sig-
nals that are output and the polarity of these outputs. The de-
fault value for the Status Register is 0 (000 Hex) for the
’ACT715/LM1882 and is “1024” (400 Hex) for the