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Linear Technology Electronic Components Datasheet


LM185H-2.5

Micropower Voltage Reference



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LM185H-2.5 pdf
December 1998
LM188254ACT715
LM1882-R54ACT715-R Programmable Video Sync
Generator
General Description
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are 20-pin
TTL-input compatible devices capable of generating Hori-
zontal, Vertical and Composite Sync and Blank signals for
televisions and monitors. All pulse widths are completely de-
finable by the user. The devices are capable of generating
signals for both interlaced and noninterlaced modes of op-
eration. Equalization and serration pulses can be introduced
into the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the system
architecture. Line rate and field/frame rate are all a function
of the values programmed into the data registers, the status
register, and the input clock frequency.
The ’ACT715/LM1882 is mask programmed to default to a
Clock Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming be-
fore operation.
The ’ACT715-R/LM1882-R is the same as the ’ACT715/
LM1882 in all respects except that the ’ACT715-R/
LM1882-R is mask programmed to default to a Clock En-
abled state. Bit 10 of the Status Register defaults to a logic
“1”. Although completely (re)programmable, the ’ACT715-R/
LM1882-R version is better suited for applications using the
default 14.31818 MHz RS-170 register values. This feature
allows power-up directly into operation, following a single
CLEAR pulse.
Features
n Maximum Input Clock Frequency > 130 MHz
n Interlaced and non-interlaced formats available
n Separate or composite horizontal and vertical Sync and
Blank signals available
n Complete control of pulse width via register
programming
n All inputs are TTL compatible
n 8 mA drive on all outputs
n Default RS170/NTSC values mask programmed into
registers
n 4 KV minimum ESD immunity
n ’ACT715-R/LM1882-R is mask programmed to default to
a Clock Enable state for easier start-up into
14.31818 MHz RS170 timing
Connection Diagrams
Pin Assignment for
DIP and SOIC
Pin Assignment
for LCC
DS100232-1
Order Number LM1882CN or LM1882CM
For Default RS-170, Order Number
LM1882-RCN or LM1882-RCM
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100232
DS100232-2
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LM185H-2.5 pdf
Logic Block Diagram
Pin Description
There are a Total of 13 inputs and 5 outputs on the ’ACT715/
LM1882.
Data Inputs D0–D7: The Data Input pins connect to the Ad-
dress Register and the Data Input Register.
ADDR/DATA: The ADDR/DATA signal is latched into the de-
vice on the falling edge of the LOAD signal. The signal deter-
mines if an address (0) or data (1) is present on the data bus.
L/HBYTE: The L/HBYTE signal is latched into the device on
the falling edge of the LOAD signal. The signal determines if
data will be read into the 8 LSB’s (0) or the 4 MSB’s (1) of the
Data Registers. A 1 on this pin when an ADDR/DATA is a 0
enables Auto-Load Mode.
LOAD: The LOAD control pin loads data into the Address or
Data Registers on the rising edge. ADDR/DATA and
L/HBYTE data is loaded into the device on the falling edge of
the LOAD. The LOAD pin has been implemented as a
Schmitt trigger input for better noise immunity.
CLOCK: System CLOCK input from which all timing is de-
rived. The clock pin has been implemented as a Schmitt trig-
ger for better noise immunity. The CLOCK and the LOAD
signal are asynchronous and independent. Output state
changes occur on the falling edge of CLOCK.
CLR: The CLEAR pin is an asynchronous input that initial-
izes the device when it is HIGH. Initialization consists of set-
ting all registers to their mask programmed values, and ini-
tializing all counters, comparators and registers. The CLEAR
pin has been implemented as a Schmitt trigger for better
noise immunity. A CLEAR pulse should be asserted by the
user immediately after power-up to ensure proper initializa-
tion of the registers — even if the user plans to (re)program
the device.
Note: A CLEAR pulse will disable the CLOCK on the ’ACT715/LM1882 and
will enable the CLOCK on the ’ACT715-R/LM1882-R.
DS100232-3
ODD/EVEN: Output that identifies if display is in odd (HIGH)
or even (LOW) field of interlace when device is in interlaced
mode of operation. In noninterlaced mode of operation this
output is always HIGH. Data can be serially scanned out on
this pin during Scan Mode.
VCSYNC: Outputs Vertical or Composite Sync signal based
on value of the Status Register. Equalization and Serration
pulses will (if enabled) be output on the VCSYNC signal in
composite mode only.
VCBLANK: Outputs Vertical or Composite Blanking signal
based on value of the Status Register.
HBLHDR: Outputs Horizontal Blanking signal, Horizontal
Gating signal or Cursor Position based on value of the Sta-
tus Register.
HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating
signal or Vertical Interrupt signal based on value of Status
Register.
Register Description
All of the data registers are 12 bits wide. Width’s of all pulses
are defined by specifying the start count and end count of all
pulses. Horizontal pulses are specified with-respect-to the
number of clock pulses per line and vertical pulses are speci-
fied with-respect-to the number of lines per frame.
REG0 — STATUS REGISTER
The Status Register controls the mode of operation, the sig-
nals that are output and the polarity of these outputs. The de-
fault value for the Status Register is 0 (000 Hex) for the
’ACT715/LM1882 and is “1024” (400 Hex) for the
’ACT715-R/LM1882-R.
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Part Number LM185H-2.5
Description Micropower Voltage Reference
Maker Linear Technology - Linear Technology
Total Page 16 Pages
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