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Integrated Device Technology Electronic Components Datasheet



ICS9LPRS535

48-pin CK505


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ICS9LPRS535 pdf
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
www.DDataaSthaeest4hU.ecoemt
48-pin CK505 for Intel Systems
Recommended Application:
48-pin Low Cost CK505 w/fully integrated VREG and series
resistors on differential outputs
Output Features:
• Integrated Series Resistors on differential outputs
• 2 - CPU differential push-pull pairs
• 4 - SRC differential push-pull pairs
• 1 - CPU/SRC selectable differential push-pull pair
• 1 - SRC/DOT selectable differential push-pull pair
• 1- SRC/Stop_Inputs selectable differential push-pull pair
• 1 - 25MHz SE1 output for Wake-on-Lan applications
• 3 - PCI, 33MHz
• 1 - USB, 48MHz
• 1 - REF, 14.31818MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/-100ppm frequency accuracy on all clocks
Features/Benefits:
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Table 1: CPU Frequency Select Table
FSLC2 FSLB1 FSLA1
B0b7 B0b6 B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
0 0 0 266.66
0 0 1 133.33
0 1 0 200.00
0 1 1 166.66 100.00 33.33 14.318 48.00
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
111
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
DOT
MHz
96.00
Pin Configuration
1461A—07/28/09
PCI0/CR#_A 1
VDDPCI 2
PCI4/SRC5_EN 3
PCI_F5/ITP_EN 4
GNDPCI 5
VDD48 6
USB_48MHz/FSLA 7
GND48 8
VDD96_IO 9
DOT96T_LPR/SRCT0_LPR 10
DOT96C_LPR/SRCC0_LPR 11
GND 12
VDD 13
SE1 14
GND 15
SRCT2_LPR/SATAT_LPR 16
SRCC2_LPR/SATAC_LPR 17
GNDSRC 18
SRCT3_LPR/CR#_C 19
SRCC3_LPR/CR#_D 20
VDDSRC_IO 21
SRCT4_LPR 22
SRCC4_LPR 23
CPU_STOP#/SRCC5_LPR 24
48 SCLK
47 SDATA
46 REF0/FSLC/TEST_SEL
45 VDDREF
44 X1
43 X2
42 GNDREF
41 FSLB/TEST_MODE
40 CK_PWRGD/PD#
39 VDDCPU
38 CPUT0_LPR
37 CPUC0_LPR
36 GNDCPU
35 CPUT1_LPR_F
34 CPUC1_LPR_F
33 VDDCPU_IO
32 CPUT2_ITP_LPR/SRCT8_LPR
31 CPUC2_ITP_LPR/SRCC8_LPR
30 VDDSRC_IO
29 SRCT7_LPR/CR#_F
28 SRCC7_LPR/CR#_E
27 GNDSRC
26 VDDSRC
25 PCI_STOP#/SRCT5_LPR
48-SSOP/TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.



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ICS9LPRS535 pdf
Integrated
Circuit
Systems, Inc.
ICS9LPRS535
www.DataSheet4U.com
Datasheet
SSOP/TSSOP Pin Description
PIN #
PIN NAME
1 PCI0/CR#_A
2 VDDPCI
3 PCI4/SRC5_EN
4 PCI_F5/ITP_EN
5 GNDPCI
6 VDD48
7 USB_48MHz/FSLA
8 GND48
9 VDD96_IO
10 DOT96T_LPR/SRCT0_LPR
11 DOT96C_LPR/SRCC0_LPR
12 GND
TYPE
DESCRIPTION
3.3V PCI clock output or CR#_A input. Default is PCI0. To configure this pin as CR#_A, the PCI output must first be disabled in
I/O Byte 2, bit 0.
Byte 5, bit 7: 0 = PCI0 enabled (default), 1= CR#_A enabled.
Byte 5, bit 6: 0 = CR#_A controls SRC0 (default), 1= CR#_A# controls SRC2.
PWR Power supply for PCI clocks, nominal 3.3V
3.3V PCI clock output / SRC5 enable strap. On powerup, the logic value on this pin determines if SRC5 or
I/O CPU_STOP#/PCI_STOP# is enabled. The latched value controls the pin function as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On
powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair.
I/O 0 =SRC8/SRC8#
1 = ITP/ITP#
PWR Ground pin for the PCI outputs
PWR Power pin for the 48MHz output.3.3V
I/O 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed
48MHz USB clock output. 3.3V.
PWR Ground pin for the 48MHz outputs
PWR Power pin for the DOT96 clocks, nominal 1.05V to 3.3V.
True clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRCT0. After
OUT powerup, this pin function may be changed to DOT96T via SMBus Byte 1, bit 7 as follows:
0= SRC0T
1=DOT96T
Complementary clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is
OUT SRC0C. After powerup, this pin function may be changed to DOT96C via SMBus Byte 1, bit 7 as follows:
0= SRC0C
1=DOT96C
PWR Ground pin.
13 VDD
14 SE1
15 GND
16 SRCT2_LPR/SATAT_LPR
17 SRCC2_LPR/SATAC_LPR
18 GNDSRC
19 SRCT3_LPR/CR#_C
20 SRCC3_LPR/CR#_D
21 VDDSRC_IO
22 SRCT4_LPR
23 SRCC4_LPR
PWR Power supply, nominal 3.3V
OUT CK505 Singled Ended Output 1. 3.3V.
PWR Ground pin.
OUT
OUT
True clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
Complementary clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor
to GND needed.
PWR Ground pin for the SRC outputs
True clock of push-pull SRC output with int. 33ohm series resistor/CR#_C input. Disable SRC3 via Byte 4, bit 7, before using as
I/O
CR#_C.
Byte 5, bit 3: 0=SRC3 (default), 1=CR#_C.
Byte 5, bit 2: 0=CR# C controls SRC0 (default), 1=CR# C controls SRC2
Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_D input. Disable SRC3 via Byte 4, bit 7,
I/O before using as CR#_D.
Byte 5, bit 1: 0=SRC3 (default),1=CR#_D.
Byte 5, bit 0: 0=CR#_D controls N/A (default), 1=CR#_D controls SRC4
PWR 1.05V to 3.3V from external power supply
OUT True clock of push-pull SRC output with int. 33ohm series resistor.
OUT Complementary clock of push-pull SRC output with int. 33ohm series resistor.
24 CPU_STOP#/SRCC5_LPR
I/O Stops all CPUCLK, except those set to be free running clocks /
Complementary clock of push-pull SRC pair with int. 33ohm series resistor.
1461A—07/28/09
2



Part Number ICS9LPRS535
Description 48-pin CK505
Maker Integrated Device Technology - Integrated Device Technology
Total Page 17 Pages
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