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ICS9LPRS464

System Clock Chip


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ICS9LPRS464 pdf
DATASHEET
System Clock Chip for ATI RS/RD600 series chipsets using
AMD CPUs
ICS9LPRS464
Description
ATI RD/RS600 series systems using AMD CPUs
Output Features
• Integrated Series Resistors on differential outputs
• Greyhound Compatible CPU outputs
• 2 - 0.7V Low Power differential CPU pairs
• 6 - 0.7V Low Power differential SRC pairs
• 2 - 0.7V Low Power differential ATIG pairs
• 1 - 66 MHz HyperTransport clock
• 2 - 48MHz USB clocks
• 3 - 14.318MHz Reference clocks
Key Specifications
• CPU outputs cycle-to-cycle jitter <150ps
• SRC outputs cycle-to-cycle jitter < 125ps
• ATIG outputs cycle-to-cycle jitter < 125ps
• +/- 100ppm frequency accuracy on all outputs if REF is
tuned to +/-100ppm
Features/Benefits:
• 3 - Programmable Clock Request pins for SRC and ATIG
clocks
• ATIGCLKs are programmable for frequency
• Spread Spectrum for EMI reduction
• Outputs may be disabled via SMBus
• External crystal load capacitors for maximum frequency
accuracy
Pin Configuration
GNDREF 1
56 FS0/REF0
VDDREF 2
55 FS1/REF1
X1 3
54 FS2/REF2
X2 4
VDD48 5
53 **PD
52 VDDHTT
48MHz_0 6
51 HTTCLK0
48MHz_1 7
50 GNDHTT
GND48 8
49 *CLKREQA#
SMBCLK 9
48 CPUKG0T_LPR
SMBDAT 10
47 CPUKG0C_LPR
RESET_IN# 11
46 VDDCPU
SRC5T_LPR 12
45 GNDCPU
SRC5C_LPR 13
44 CPUKG1T_LPR
VDDSRC 14
43 CPUKG1C_LPR
GNDSRC 15
42 VDDA
SRC4T_LPR 16
41 GNDA
SRC4C_LPR 17
40 NC
SRC3T_LPR 18
39 SRC0T_LPR
SRC3C_LPR 19
38 SRC0C_LPR
SRC2T_LPR 20
37 GNDSRC
SRC2C_LPR 21
36 VDDSRC
GNDSRC 22
35 ATIG0T_LPR
VDDSRC 23
34 ATIG0C_LPR
SRC1T_LPR 24
33 VDDATIG
SRC1C_LPR 25
32 GNDATIG
VDDSRC 26
31 ATIG1T_LPR
GNDSRC 27
30 ATIG1C_LPR
*CLKREQB# 28
29 *CLKREQC#
56-Pin SSOP/TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Power Groups
Pin Number
VDD
5
GND
8
14,23,26,36 15,22,27,37
33 32
42 41
46 45
52 50
Description
USB_48 outputs
SRCCLK outputs
ATIGCLK differential outputs
Analog, PLL
CPUCLK8 differential outputs
HTTCLK output
21
REF outputs
Funtionality
FS2 FS1 FS0
000
001
010
011
100
101
110
111
CPU
MHz
Hi-Z
X/2
230.00
240.00
100.00
133.33
166.67
200.00
HTT
MHz
Hi-Z
X/3
76.67
80.00
66.66
66.66
66.66
66.66
SRC
M Hz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
ATIG
M Hz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
USB
M Hz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
1
1377A—04/07/08
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ICS9LPRS464 pdf
ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
Pin Description
PIN #
PIN NAME
1 GNDREF
2 VDDREF
3 X1
4 X2
5 VDD48
6 48MHz_0
7 48MHz_1
8 GND48
9 SMBCLK
10 SMBDAT
11 RESET_IN#
12 SRC5T_LPR
13 SRC5C_LPR
14 VDDSRC
15 GNDSRC
16 SRC4T_LPR
17 SRC4C_LPR
18 SRC3T_LPR
19 SRC3C_LPR
20 SRC2T_LPR
21 SRC2C_LPR
22 GNDSRC
23 VDDSRC
24 SRC1T_LPR
25 SRC1C_LPR
26 VDDSRC
27 GNDSRC
28 *CLKREQB#
TYPE
GND
PWR
IN
OUT
PWR
OUT
OUT
GND
IN
I/O
IN
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
PWR
GND
IN
DESCRIPTION
Ground pin for the REF outputs.
Ref, XTAL power supply, nominal 3.3V
Crystal input, nominally 14.318MHz
Crystal output, nominally 14.318MHz
Power pin for the 48MHz outputs and core. 3.3V
48MHz clock output.
48MHz clock output.
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Real Time falling edge triggered input, When asserted, the part initiates a power
up reset with the SMBus being reset to it's power up values, and all PLL derived
clocks stopped for the duration of Power up Stabilization. REF outputs continue
to run.
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33
ohm series resistor. (no 50ohm shunt resistor to GND needed)
Supply for SRC, 3.3V nominal
Ground pin for the SRC outputs
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33
ohm series resistor. (no 50ohm shunt resistor to GND needed)
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33
ohm series resistor. (no 50ohm shunt resistor to GND needed)
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33
ohm series resistor. (no 50ohm shunt resistor to GND needed)
Ground pin for the SRC outputs
Supply for SRC, 3.3V nominal
True clock of low power differential SRC clock pair with integrated 33 ohm series
resistor. (no 50ohm shunt resistor to GND needed)
Complement clock of low power differential SRC clock pair with integrated 33
ohm series resistor. (no 50ohm shunt resistor to GND needed)
Supply for SRC, 3.3V nominal
Ground pin for the SRC outputs
Programmable Clock Request pin for SRC/ATIG/SB_SRC outputs. If output is
selected for control, then that output is controlled as follows:
0 = Enabled, 1 = Tri-state
IDTTM/ICSTM System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
2
1377A—04/07/08



Part Number ICS9LPRS464
Description System Clock Chip
Maker Integrated Device Technology - Integrated Device Technology
Total Page 23 Pages
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