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Integrated Device Technology Electronic Components Datasheet



ICS9LP525-2

56-pin CK505



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ICS9LP525-2 pdf
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DATASHEET
56-pin CK505 for Intel Desktop Systems
ICS9LP525-2
Recommended Application:
CK505 clock, 56-pin Intel Yellow Cover part
Output Features:
• 2 - CPU differential low power push-pull pairs
• 7- SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull pair
• 1 - SRC/DOT selectable differential low power push-pull pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on all outputs
• SRC are PCIe Gen2 compliant
Features/Benefits:
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Selectable SRC differential push-pull pair/two single
ended outputs
Table 1: CPU Frequency Select Table
FSLC2
B0b7
0
0
0
0
1
1
1
1
FSLB1
B0b6
0
0
1
1
0
0
1
1
FSLA1
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC PCI REF USB DOT
MHz MHz MHz MHz MHz
100.00 33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
IDT® PC MAIN CLOCK
PCI0/CR#_A 1
56 SCLK
VDDPCI 2
55 SDATA
PCI1/CR#_B 3
PCI2/TME 4
PCI3/CFG0 5
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96_IO 12
DOTT_96/SRCT0 13
DOTC_96/SRCC0 14
GND 15
VDD 16
SRCT1/SE1 17
SRCC1/SE2 18
GND 19
VDDPLL3_IO 20
SRCT2/SATAT 21
SRCC2/SATAC 22
GNDSRC 23
SRCT3/CR#_C 24
SRCC3/CR#_D 25
VDDSRC_IO 26
SRCT4 27
SRCC4 28
54 REF0/FSLC/TEST_SEL
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUT0
45 CPUC0
44 GNDCPU
43 CPUT1_F
42 CPUC1_F
41 VDDCPU_IO
40 VOUT
39 CPUT2_ITP/SRCT8
38 CPUC2_ITP/SRCC8
37 VDDSRC_IO
36 SRCT7/CR#_F
35 SRCC7/CR#_E
34 GNDSRC
33 SRCT6
32 SRCC6
31 VDDSRC
30 PCI_STOP#/SRCT5
29 CPU_STOP#/SRCC5
56-SSOP & TSSOP
1
1397—11/08/10



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ICS9LP525-2
PC MAIN CLOCK
Pin Description
PIN #
PIN NAME
1 PCI0/CR#_A
2 VDDPCI
3 PCI1/CR#_B
4 PCI2/TME
5 PCI3/CFG0
6 PCI4/SRC5_EN
7 PCI_F5/ITP_EN
8 GNDPCI
9 VDD48
10 USB_48MHz/FSLA
11 GND48
12 VDD96_IO
13 DOTT_96/SRCT0
14 DOTC_96/SRCC0
15 GND
16 VDD
17 SRCT1/SE1
18 SRCC1/SE2
19 GND
20 VDDPLL3_IO
21 SRCT2/SATAT
22 SRCC2/SATAC
23 GNDSRC
TYPE
I/O
PWR
I/O
I/O
I/O
I/O
I/O
PWR
PWR
I/O
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via
SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address
space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or
pair 0 using the CRA#_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CRA# enabled. Byte 5, bit 6 controls whether CRA# controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CRA# controls SRC0 pair (default),
1= CRA# controls SRC2 pair
Power supply for PCI clocks, nominal 3.3V
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via
SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address
space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or
pair 4 using the CRB#_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CRB# enabled. Byte 5, bit 6 controls whether CRB# controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CRB# controls SRC1 pair (default)
1= CRB# controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows
0=Overclocking of CPU and SRC allowed
1=Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output/Configuration Strap. See PCI3 Configuration Table for more information
3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if
the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on
pins 29 and 30 as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On
powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground pin for the PCI outputs
Power pin for the 48MHz output and PLL.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed
48MHz USB clock output. 3.3V.
Ground pin for the 48MHz outputs
Power supply for DOT96 clocks, nominal 0.8V from source/emitter of external pass transistor.
True clock of low power differential SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be
changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
Complement clock of low power differential SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin
function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
Ground pin.
Power supply, nominal 3.3V
True clock of low power differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5%
downspread. The pin function may be changed via SMBus B1b[4:1]
Complement clock of push-pull differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -
0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Ground pin.
Power supply for PLL3. 0.8V nominal from source/emitter of external pass transistor
True clock of low power differentiall SRC/SATA clock pair.
Complement clock of differential push-pull SRC/SATA clock pair.
Ground pin for the SRC outputs
IDTTM/ICSTM PC MAIN CLOCK
2
1397—11/08/10



Part Number ICS9LP525-2
Description 56-pin CK505
Maker Integrated Device Technology - Integrated Device Technology
Total Page 21 Pages
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