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ICS9FG1201H

Frequency Generator



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ICS9FG1201H pdf
DATASHEET
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered
DIMM Clocks
ICS9FG1201H
Description
Features/Benefits
ICS9FG1201 follows the Intel DB1200G Differential Buffer
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCI Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410 or CK410B main clock generator,
such as the ICS954101 or ICS932S401, drives the ICS9FG1201.
ICS9FG1201 can provide outputs up to 400MHz.
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(11:10) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 50ps within a group
• DIF output-to-output skew < 100ns across all outputs
• 56-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Funtional Block Diagram
OE#
OE(9:0)#
10
SPREAD
COMPATIBLE
PLL
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
PLL
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(11:10)
GEAR
SHIFT
LOGIC
STOP
LOGIC
10
DIF(9:0)
IREF
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
1
ICS9FG1201H 10/22/07



No Preview Available !

ICS9FG1201H pdf
ICS9FG1201H
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
Pin Configuration
HIGH_BW# 1
56 VDDA
CLK_IN 2
55 GNDA
CLK_IN# 3
54 IREF
SMB_A0 4
53 OE10_11#
OE0# 5
52 DIF_11
DIF_0 6
51 DIF_11#
DIF_0# 7
50 VDD
OE1# 8
49 GND
DIF_1 9
48 DIF_10
DIF_1# 10
47 DIF_10#
VDD 11
46 FS_A_410
GND 12
45 VTT_PWRGD#/PD
DIF_2 13
44 OE9#
DIF_2# 14
43 DIF_9
OE2# 15
42 DIF_9#
DIF_3 16
41 OE8#
DIF_3# 17
40 DIF_8
OE3# 18
39 DIF_8#
DIF_4 19
38 VDD
DIF_4# 20
37 GND
OE4# 21
36 DIF_7
VDD 22
35 DIF_7#
GND 23
34 OE7#
DIF_5 24
33 DIF_6
DIF_5# 25
32 DIF_6#
OE5# 26
31 OE6#
SMB_A1 27
30 SMB_A2_PLLBYP#
SMBDAT 28
29 SMBCLK
56-pin SSOP & TSSOP
Functionality Table
FS_A_4101
1
1
1
1
0
0
0
0
CLK_IN (CPU FSB)
MHz
100.00
133.33
166.66
200.00
266.66
333.33
400.00
DIF_(9:0) Output
MHz
100.00
133.33
166.66
RESERVED
200.00
266.66
333.33
400.00
DIF_(11:10) Output
MHz
100.00
133.33
166.66
200.00
266.66
333.33
400.00
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDTTM/ICSTM Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
2
ICS9FG1201H 10/22/07



Part Number ICS9FG1201H
Description Frequency Generator
Maker IDT - IDT
Total Page 21 Pages
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ICS9FG1201H pdf
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