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Integrated Device Technology Electronic Components Datasheet



ICS9FG1200D-1

Frequency Gearing Clock



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ICS9FG1200D-1 pdf
DATASHEET
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2
& FBD
ICS9FG1200D-1
Description
ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCIe Gen2, or Fully Buffered DIMM applications.The outputs
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1200D-1. The
ICS9FG1200D-1 can provide outputs up to 400MHz.
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 100ps across all outputs in 1:1
mode
• 56-pin SSOP/TSSOP package
• RoHS compliant packaging
Features/Benefits
• Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
• Power up default is all outputs in 1:1 mode
• DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
• DIF_(11:10) can be “gear-shifted” from the input CPU
Host Clock
• Spread spectrum compatible
• Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Functional Block Diagram
OE#
OE(9:0)#
10
SPREAD
COMPATIBLE
1:1 PLL
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
GEARING PLL
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
STOP
LOGIC
2
DIF(11:10)
STOP
LOGIC
10
DIF(9:0)
IREF
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1
1138C 02/08/10



No Preview Available !

ICS9FG1200D-1 pdf
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Pin Configuration
Power Groups
Pin Number
VDD
GND
56
11,22,38,50
55
12,23,37,49
HIGH_BW# 1
CLK_IN 2
CLK_IN# 3
SMB_A0 4
OE0# 5
DIF_0 6
DIF_0# 7
OE1# 8
DIF_1 9
DIF_1# 10
VDD 11
GND 12
DIF_2 13
DIF_2# 14
OE2# 15
DIF_3 16
DIF_3# 17
OE3# 18
DIF_4 19
DIF_4# 20
OE4# 21
VDD 22
GND 23
DIF_5 24
DIF_5# 25
OE5# 26
SMB_A1 27
SMBDAT 28
56 VDDA
55 GNDA
54 IREF
53 OE10_11#
52 DIF_11
51 DIF_11#
50 VDD
49 GND
48 DIF_10
47 DIF_10#
46 FS_A_410
45 VTT_PWRGD#/PD
44 OE9#
43 DIF_9
42 DIF_9#
41 OE8#
40 DIF_8
39 DIF_8#
38 VDD
37 GND
36 DIF_7
35 DIF_7#
34 OE7#
33 DIF_6
32 DIF_6#
31 OE6#
30 SMB_A2_PLLBYP#
29 SMBCLK
56-pin SSOP & TSSOP
Description
Main PLL, Analog
DIF clocks
Functionality at Power Up (PLL Mode)
FS_A_4101
CLK_IN (CPU FSB)
MHz
DIF_(11:0)
MHz
1
100 <= CLK_IN < 200
CLK_IN
0
200<= CLK_IN <= 400
CLK_IN
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
2
1138C 02/08/10



Part Number ICS9FG1200D-1
Description Frequency Gearing Clock
Maker IDT - IDT
Total Page 23 Pages
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ICS9FG1200D-1 pdf
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