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ICS9DB102

Two Output Differential Buffer



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ICS9DB102 pdf
Two Output Differential Buffer for PCIe Gen1 & Gen2
DATASHEET
ICS9DB102
Description
The ICS9DB102 zero-delay buffer supports PCI Express
clocking requirements. The ICS9DB102 is driven by a differential
SRC output pair from an ICS CK410/CK505-compliant main
clock. It attenuates jitter on the input clock and has a selectable
PLL Band Width to maximize performance in systems with or
without Spread-Spectrum clocking.
Output Features
• 2 - 0.7V current mode differential output pairs (HCSL)
Features/Benefits
• CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Industrial temperature range available
Key Specifications
• Cycle-to-cycle jitter < 35ps
• Output-to-output skew < 25ps
Functional Block Diagram
CLKREQ0#
CLKREQ1#
CLK_INT
C LK_IN C
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
PCIEX0
PCIEX1
IREF
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
1
852 REV K 04/01/10



No Preview Available !

ICS9DB102 pdf
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Pin Configuration
PLL_BW 1
CLK_INT 2
CLK_INC 3
**CLKREQ0# 4
VDD 5
GND 6
PCIEXT0 7
PCIEXC0 8
VDD 9
SMBDAT 10
20 VDDA
19 GNDA
18 IREF
17 **CLKREQ1#
16 VDD
15 GND
14 PCIEXT1
13 PCIEXC1
12 VDD
11 SMBCLK
Note: Pins preceeded by '**' have internal
120K ohm pull down resistors
20-pin SSOP & TSSOP
Power Groups
Pin Number
VDD
GND
5,9,12,16
6,15
96
20 19
20 19
Description
PCI Express Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
Pin Description
PIN #
PIN NAME
1 PLL_BW
2 CLK_INT
3 CLK_INC
4 **CLKREQ0#
5 VDD
6 GND
7 PCIEXT0
8 PCIEXC0
9 VDD
10 SMBDAT
11 SMBCLK
12 VDD
13 PCIEXC1
14 PCIEXT1
15 GND
16 VDD
17 **CLKREQ1#
18 IREF
19 GNDA
20 VDDA
PIN TYPE
INPUT
INPUT
INPUT
INPUT
POWER
POWER
OUTPUT
OUTPUT
POWER
I/O
INPUT
POWER
OUTPUT
OUTPUT
POWER
POWER
INPUT
OUTPUT
POWER
POWER
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = low, 1= high
"True" reference clock input.
"Complementary" reference clock input.
Output enable for SRC/PCI Express output pair '0'
0 = enabled, 1 = tri-stated
Power supply, nominal 3.3V
Ground pin.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply, nominal 3.3V
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Ground pin.
Power supply, nominal 3.3V
Output enable for SRC/PCI Express output pair '1'
0 = enabled, 1 = tri-stated
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
Note:
Pins preceeded by '**' have internal 120K ohm pull down resistors
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
2
852 REV K 04/01/10



Part Number ICS9DB102
Description Two Output Differential Buffer
Maker IDT - IDT
Total Page 13 Pages
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