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Integrated Device Technology Electronic Components Datasheet



ICS98ULPA877A

1.8V Low-Power Wide-Range Frequency Clock Driver



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ICS98ULPA877A pdf
Integrated
Circuit
Systems, Inc.
ICS98UL PA8 77A
Advance Informationwww.DataSheet4U.com
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application:
• DDR2 Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR2 DIMM logic solution
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667/800)
• OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• CYCLE - CYCLE jitter 40ps
Block Diagram
Pin Configuration
123456
A
B
C
D
E
F
G
H
J
K
1
A CLKT1
B CLKC1
C CLKC2
D CLKT2
E CLK_INT
F CLK_INC
G AGND
H AVDD
J CLKT3
K CLKC3
2
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
52-Ball BGA
Top View
3
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
5
CLKT5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
CLKC9
6
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
OE
OS
AVDD
(1)
LD or OE
POWER
DOWN
AND LD, OS, or OE
TEST
MODE
LOGIC
PLL BYPASS
LD
CLK_INT
CLK_INC
10KΩ - 100KΩ
FBIN_INT
FBIN_INC
PLL
NOTE:
1. The Logic Detect (LD) powers down the device
when a logic LOW is applied to both CLK_INT and
CLK_INC.
1177C—05/23/07
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FBOUTT
FBOUTC
VDDQ
CLKC2
CLKT2
CLK_INT
CLK_INC
VDDQ
AGND
AVDD
VDDQ
GND
1
2
3
4
5
6
7
8
9
10
40-Pin MLF
30 CLKC7
29 CLKT7
28 VDDQ
27 FB_INT
26 FB_INC
25 FBOUTC
24 FBOUTT
23 VDDQ
22 OE
21 OS
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.



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ICS98ULPA877A pdf
ICS98UL PA8 77A
Advance Information
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Pin Descriptions
Terminal
Name
AGND
AVDD
CLK_INT
CLK_INC
FB_INT
FB_INC
FB_OUTT
FB_OUTC
OE
OS
GND
VDDQ
CLKT[0:9]
CLKC[0:9]
NB
Description
Analog Ground
Analog power
Clock input with a (10K-100K Ohm) pulldown resistor
Complentary clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Complementary feedback clock input
Feedback clock output
Complementary feedback clock output
Output Enable (Asynchronous)
Output Select (tied to GND or VDDQ)
Ground
Logic and output power
Clock outputs
Complementary clock outputs
No ball
Electrical
Characteristics
Ground
1.8 V nominal
Differential input
Differential input
Differential input
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
1.8V nominal
Differential outputs
Differential outputs
The PLL clock buffer, ICS98ULPA877A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and
output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS98ULPA877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or VDDQ.When OS is high, OE will function as described above.When
OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC).When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF.When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time tSTAB.
The PLL in ICS98ULPA877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).
ICS98ULPA877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
1177C—05/23/07
2



Part Number ICS98ULPA877A
Description 1.8V Low-Power Wide-Range Frequency Clock Driver
Maker Integrated Device Technology - Integrated Device Technology
Total Page 14 Pages
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