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ICS8S89834I

2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer



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ICS8S89834I pdf
Low Skew, 2-to-4 LVCMOS/LVTTL-to-
LVPECL/ECL Clock Multiplexer
ICS8S89834I
DATA SHEET
General Description
The ICS8S89834I is a high speed 2-to-4
ICS LVCMOS/LVTTL-to-LVPECL/ECL Clock Multiplexer.
HiPerClockS™ The ICS8S89834I is optimized for high speed and very
low output skew, making it suitable for use in
demanding applications such as SONET, 1 Gigabit
and 10 Gigabit Ethernet, and Fibre Channel. The device also has an
output enable pin which may be useful for system test and debug
purposes. The ICS8S89834I is packaged in a small 3mm x 3mm
16-pin VFQFN package which makes it ideal for use in
space-constrained applications.
Features
Four differential LVPECL/ECL output pairs
Two LVCMOS/LVTTL clock inputs
Maximum output frequency: 1GHz
Output skew: 30ps (maximum)
Part-to-part skew: 100ps (maximum)
Propagation delay: 550ps (maximum)
Additive phase jitter, RMS: 0.12ps (typical)
Full 3.3V and 2.5V operating supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
SEL Pullup
IN1 Pullup
IN2 Pullup
1
0
EN Pullup
DQ
CK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q1 1
12 IN1
nQ1 2
11 SEL
Q2 3
10 nc
nQ2 4
9 IN2
5 6 78
ICS8S89834I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
1
©2010 Integrated Device Technology, Inc.



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ICS8S89834I pdf
ICS8S89834I Data Sheet
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
Type
Output
Output
Output
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
7, 14
8
9
10
11
12
13
15, 16
Vcc
EN
IN2
nc
SEL
IN1
VEE
Q0, nQ0
Power
Input
Input
Unused
Input
Input
Power
Output
Pullup
Pullup
Pullup
Pullup
Positive supply pins.
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is VCC/2V. Includes a
37kpullup resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN1, IN2.
LVTTL/LVCMOS interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
No connect.
Select clock input. When LOW, selects IN2 and when HIGH selects IN1.
LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
RPULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
2
©2010 Integrated Device Technology, Inc.



Part Number ICS8S89834I
Description 2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer
Maker IDT - IDT
Total Page 17 Pages
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