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ICS8S89832I

1-to-4 Differential-to-LVDS Fanout Buffer



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ICS8S89832I pdf
Low Skew, 1-to-4 Differential-to-LVDS
Fanout Buffer
ICS8S89832I
DATA SHEET
General Description
The ICS8S89832I is a high speed 1-to-4
ICS Differential-to-LVDS Fanout Buffer. The ICS8S89832I
HiPerClockS™ is optimized for high speed and very low output skew,
making it suitable for use in demanding applications
such as SONET, 1 Gigabit and 10 Gigabit Ethernet,
and Fibre Channel. The internally terminated differential input and
VREF_AC pin allow other differential signal families such as LVPECL,
LVDS, and SSTL to be easily interfaced to the input with minimal use
of external components. The device also has an output enable pin
which may be useful for system test and debug purposes. The
ICS8S89832I is packaged in a small 3mm x 3mm 16-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
Features
Four differential LVDS output pairs
IN, nIN input pairs can accept the following differential input levels:
LVPECL, LVDS, SSTL
50internal input termination to VT
Maximum output frequency: 2GHz
Output skew: 25ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation delay: 550ps (maximum)
Additive phase jitter, RMS: 0.09ps (typical)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN
50
VT
50
nIN
VREF_AC
EN
DQ
CLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q1 1
12 IN
nQ1 2
11 VT
Q2 3
10 VREF_AC
nQ2 4
9 nIN
5 6 78
ICS8S89832I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89832AKI REVISION A JANUARY 11, 2010
1
©2010 Integrated Device Technology, Inc.



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ICS8S89832I pdf
ICS8S89832I Data Sheet
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
Type
Output
Output
Output
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
7, 14
8
9
10
11
12
13
15, 16
VDD
EN
nIN
VREF_AC
VT
IN
GND
Q0, nQ0
Power
Input
Input
Output
Input
Input
Power
Output
Pullup
Positive supply pins.
Synchronizing clock enable. When LOW, Qx outputs will go LOW and nQx outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is VDD/2V. Includes a
37kpullup resistor. Default state is HIGH when left floating. The internal latch is
clocked on the falling edge of the input signal IN. See Table 3A
LVTTL / LVCMOS interface levels.
Inverting differential clock input. 50internal input termination to VT.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting differential clock input. 50internal input termination to VT.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
37
Maximum
Units
pF
k
ICS8S89832AKI REVISION A JANUARY 11, 2010
2
©2010 Integrated Device Technology, Inc.



Part Number ICS8S89832I
Description 1-to-4 Differential-to-LVDS Fanout Buffer
Maker IDT - IDT
Total Page 16 Pages
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