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Integrated Device Technology Electronic Components Datasheet



ICS889872

DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION



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PRELIMINARY
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER
W/INTERNAL TERMINATION
ICS889872
General Description
The ICS889872 is a high speed Differential-to-
ICS LVDS Buffer/Divider w/Internal Termination and is a
HiPerClockS™ member of the HiPerClockS™family of high
performance clock solutions from IDT. The
ICS889872 has a selectable ÷2, ÷4, ÷8, ÷16 output
dividers. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
Three LVDS outputs
Frequency divide select options: ÷4, ÷6: >2GHz,
÷8, ÷16: >1.6GHz
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: >2GHz
Cycle-to-cycle jitter: 1ps (typical)
Total jitter: 10ps (typical)
Output skew: 7ps (typical), QA/nQA outputs
Part-to-part skew: 250ps (typical)
Propagation Delay: 750ps (typical), QA/nQA outputs
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
nRESET/
nDISABLE
Enable
FF
Enable
MUX
IN
50
VT
50
nIN
VREF_AC
S1
S0
Decoder
÷2, ÷4,
÷8, ÷16
QA
nQA
QB0
nQB0
QB1
nQB1
16 15 14 13
QB0 1
12 IN
nQB0 2
11 VT
QB1 3
10 VREF_AC
nQB1 4
9 nIN
5 6 78
ICS889872
16-Lead VFQFN
3mm x 3mm x 0.95mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
1
ICS889872AK REV. A AUGUST 22, 2007



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ICS889872 pdf
ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 2
Name
QB0, nQB0
Type
Output
3, 4 QB1, nQB1 Output
5, 6
QA, nQA
Output
Description
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB0/nQB0).
LVDS interface levels.
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB1nQB1).
LVDS interface levels.
Differential undivided output pair. LVDS interface levels.
7, 14
8
9
10
11
12
13
15, 16
VDD
nRESET/
nDISABLE
nIN
VREF_AC
VT
IN
GND
S1, S0
Power
Input
Input
Output
Input
Input
Power
Input
Pullup
Pullup
Power supply pins.
Output reset and enable/disable pin. When LOW, resets the divider select,
and align Bank A and Bank B edges. In addition, when LOW, Bank A and
Bank B will be disabled. Input threshold is VDD/2V.
Includes a 37kpullup resistor. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50termination to VT.
Reference voltage for AC-coupled applications. Equal to VDD – 1.4V
(approx.). Maximum sink/source current is 0.5mA.
Termination input. Leave pin floating.
Non-inverting LVPECL differential clock input.
RT = 50termination to VT.
Power supply ground.
Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB.
Input threshold is VDD/2. 37kW pullup resistor.
LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
RPULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
2
ICS889872AK REV. A AUGUST 22, 2007



Part Number ICS889872
Description DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Maker IDT - IDT
Total Page 14 Pages
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