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Integrated Device Technology Electronic Components Datasheet



ICS889832

1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER



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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-
LVDS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS889832 is a high speed 1-to-4 Differential-
ICS to-LVDS Fanout Buffer and is a member of the
HiPerClockS™ HiPerClockS™ family of high performance clock
solutions from IDT. The ICS889832 is optimized
for high speed and very low output skew, making
it suitable for use in demanding applications such as SONET,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and VREF_AC pin allow
other differential signal families such as LVPECL, LVDS, and
SSTL to be easily interfaced to the input with minimal use of
external components. The device also has an output enable
pin which may be useful for system test and debug purposes.
The ICS889832 is packaged in a small 3mm x 3mm 16-pin
VFQFN package which makes it ideal for use in space-
constrained applications.
ICS889832
FEATURES
Four differential LVDS outputs
IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, SSTL
50
internal
input
termination
to
V
T
Output frequency: >2GHz
Output skew: 25ps (maximum)
Part-to-part skew: 200ps (maximum)
Additive phase jitter, RMS: <0.2ps (typical)
Propagation delay: 510ps (maximum)
2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
IN
50
VT
50
nIN
VREF_AC
EN
DQ
PIN ASSIGNMENT
16 15 14 13
Q0
Q1 1
12 IN
nQ0
nQ1 2
11 VT
Q2 3
10 VREF_AC
Q1
nQ2 4
9 nIN
5678
nQ1
Q2 ICS889832
nQ2 16-Lead VFQFN
3mm x 3mm x 0.95 package body
Q3 K Package
Top View
nQ3
IDT/ ICSLVDS FANOUT BUFFER
1 ICS889832AK REV A SEPTEMBER 19, 2006



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ICS889832 pdf
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2 Q1, nQ1 Output
Differential output pair. LVDS interface levels.
3, 4 Q2, nQ2 Output
Differential output pair. LVDS interface levels.
5, 6 Q3, nQ3 Output
Differential output pair. LVDS interface levels.
7, 14
8
9
10
11
12
13
VDD
EN
nIN
VREF_AC
VT
IN
GND
Power
Input
Input
Output
Input
Input
Power
Pullup
Positive supply pins.
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ
outputs will go HIGH on the next LOW transition at IN inputs. Input
threshold is VDD/2V. Includes a 37kpull-up resistor. Default state is
HIGH when left floating. The internal latch is clocked on the falling edge
of the input signal IN. LVTTL / LVCMOS interface levels.
Inverting differential clock input. 50internal input termination to VT.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting
differential
clock
input.
50
internal
input
termination
to
V.
T
Power supply ground.
15, 16
Q0, nQ0 Output
Differential output pair. LVDS interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
RPULLUP Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum Units
k
IDT/ ICSLVDS FANOUT BUFFER
2 ICS889832AK REV A SEPTEMBER 19, 2006



Part Number ICS889832
Description 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER
Maker IDT - IDT
Total Page 15 Pages
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