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ICS874S02I

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR


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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS874S02I
General Description
The ICS874S02I is a highly versatile 1:1 Differential-
ICS to-LVDS Clock Generator and a member of the
HiPerClockS™ HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS874S02I has a fully
integrated PLL and can be configured as a zero
delay buffer, multiplier or divider, and has an output frequency
range of 62.5MHz to 1GHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output
dividers.
Features
One differential LVDS output pair and
one differential feedback output pair
One differential clock input pair
CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL
Input frequency range: 62.5MHz to 1GHz
Output frequency range: 62.5MHz to 1GHz
VCO range: 500MHz - 1GHz
External feedback for "zero delay" clock regeneration with
configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 35ps (maximum)
Static phase offset: ±100ps
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in standard (RoHS 5) package
Block Diagram
PLL_SEL Pullup
CLK Pulldown
nCLK Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
PLL
FB_IN Pulldown
nFB_IN Pullup
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
SEL0 Pulldown
SEL1 Pulldown
SEL2 Pulldown
SEL3 Pulldown
MR Pulldown
IDT™ / ICS™ LVDS CLOCK GENERATOR
Q
nQ
QFB
nQFB
Pin Assignment
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
9
10
20 SEL1
19 SEL0
18 VDD
17 PLL_SEL
16 VDDA
15 SEL3
14 GND
13 Q
12 nQ
11 VDDO
ICS874S02I
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
1 ICS874S02BMI REV. AOCTOBER 16, 2008



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ICS874S02I pdf
ICS874S02I
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1 CLK Input Pulldown Non-inverting differential clock input.
2
nCLK
Input
Pullup Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
3
MR
Input
Pulldown
causing the true outputs Q and QFB to go low and the inverted outputs nQ and
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
4
nFB_IN
Input
Pullup
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.” Connect to pin 8.
5
FB_IN
Input
Pulldown
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 9.
6, 15,
19, 20
SEL2, SEL3,
SEL0, SEL1
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
7, 11
8, 9
VDDO
nQFB, QFB
Power
Output
Output supply pins.
Differential feedback output pair. HSTL interface levels.
10, 14
GND
Power
Power supply ground.
12, 13
nQ, Q
Output
Differential clock output pair. HSTL interface levels.
16
VDDA
Power
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
17
PLL_SEL
Input
Pullup dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
18 VDD Power
Core supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
k
IDT™ / ICS™ LVDS CLOCK GENERATOR
2 ICS874S02BMI REV. AOCTOBER 16, 2008



Part Number ICS874S02I
Description 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Maker IDT - IDT
Total Page 16 Pages
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