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ICS8745BI-21

1:1 Differential-to-LVDS Zero Delay Clock Generator



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ICS8745BI-21 pdf
1:1 Differential-to-LVDS Zero Delay
Clock Generator
ICS8745BI-21
DATA SHEET
General Description
Features
The ICS8745BI-21 is a highly versatile 1:1 LVDS Clock Generator.
The ICS8745BI-21 has a fully integrated PLL and can be configured
as a zero delay buffer, multiplier or divider, and has an output
frequency range of 31.25MHz to 700MHz. The Reference Divider,
Feedback Divider and Output Divider are each programmable,
thereby allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the
device to achieve “zero delay” between the input clock and the
output clock. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output dividers.
Pin Assignments
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
VDDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
9
10
20 SEL1
19 SEL0
18 VDD
17 PLL_SEL
16 VDDA
15 SEL3
14 GND
13 Q
12 nQ
11 VDDO
ICS8745BI-21
One differential LVDS output designed to meet
or exceed the requirements of ANSI TIA/EIA-644
One differential feedback output pair
Differential CLK, nCLK input pair
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 30ps (maximum)
Output skew: 40ps (maximum)
Static phase offset: 25ps ± 125ps
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
Block Diagram
PLL_SEL Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32,÷64
0
Q
nQ
CLK Pulldown
nCLK Pullup
1 QFB
nQFB
32 31 30 29 28 27 26 25
SEL0 1
24 GND
SEL1
nc
nc
CLK
nCLK
nc
2 ICS8745BI-21 23
3 32 Lead VFQFN 22
4 5mm x 5mm x 0.925mm 21
5 package body 20
6 K Package 19
7 Top View 18
Q
nQ
VDDO
GND
QFB
nQFB
MR 8
17 VDDO
9 10 11 12 13 14 15 16
FB_IN Pulldown
nFB_IN Pullup
SEL0 Pulldown
SEL1 Pulldown
SEL2 Pulldown
SEL3 Pulldown
MR Pulldown
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
ICS8745BMI-21 REVISION D JULY 28, 2010
1
©2010 Integrated Device Technology, Inc.



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ICS8745BI-21 pdf
ICS8745BI-21 Data Sheet
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1 CLK Input Pulldown Non-inverting differential clock input.
2
nCLK
Input
Pullup Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
3
MR
Input
Pulldown
causing the true output Q to go low and the inverted output nQ to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
4
nFBIN
Input
Pullup
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
5
FBIN
Input
Pulldown
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
6, 15,
19, 20
SEL2, SEL3,
SEL0 SEL1
Input
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
7, 11
8, 9
VDDO
nQFB/QFB
Power
Output
Output supply pins.
Differential feedback output pair. LVDS interface levels.
10, 14
GND
Power
Power supply ground.
12, 13
nQ/Q
Output
Differential output pair. LVDS interface levels.
16
VDDA
Power
Analog supply pin.
17
PLL_SEL
Input
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels.
18 VDD Power
Core supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS8745BMI-21 REVISION D JULY 28, 2010
2
©2010 Integrated Device Technology, Inc.



Part Number ICS8745BI-21
Description 1:1 Differential-to-LVDS Zero Delay Clock Generator
Maker Integrated Device Technology - Integrated Device Technology
Total Page 21 Pages
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