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Integrated Device Technology Electronic Components Datasheet



ICS874005-04

PCI EXPRESS JITTER ATTENUATOR



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ICS874005-04 pdf
PCI EXPRESS™ JITTER ATTENUATOR
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ICS874005-04
GENERAL DESCRIPTION
The ICS874005-04 is a high performance Diff-
ICS erential-to-LVDS Jitter Attenuator designed for use
HiPerClockS™ in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The
ICS874005-04 has 2 PLL bandwidth modes: 300kHz and
2MHz. The 300kHz mode will provide maximum jitter
attenuation, but higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. The 2MHz bandwidth provides the best tracking
skew and will pass most spread profiles. The ICS874005-04
supports Serdes reference clock frequencies of 100MHz,
125MHz and 250MHz.
The ICS874005-04 uses IDT’s 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
BLOCK DIAGRAM
OEA Pullup
F_SELA Pulldown
BW_SEL Pulldown
0 = ~300kHz
1 = ~2MHz
CLK Pulldown
nCLK Pullup
Phase
Detector
VCO
490 - 640MHz
M = ÷5 (fixed)
F_SELA
0 ÷5 (default)
1 ÷4
F_SELB
0 ÷2 (default)
1 ÷4
F_SELB Pulldown
MR Pulldown
OEB Pullup
FEATURES
Five differential LVDS output pairs
One differential clock input
Supports 100MHz, 125MHz, and 250MHz Serdes reference
clocks
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 320MHz
Input frequency range: 98MHz - 128MHz
• PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
RMS phase jitter @ 100MHz (1.875MHz – 20MHz):
0.88ps (typical)
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4
3.3V operating supply
Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
PLL BANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~300kHz (default)
1 = PLL Bandwidth: ~2MHz
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
QB2
nQB2
PIN ASSIGNMENT
nQB2
nQA1
QA1
VDDO
QA0
nQA0
MR
BW_SEL
VDDA
F_SELA
VDD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24 QB2
23 VDDO
22 QB1
21 nQB1
20 QB0
19 nQB0
18 F_SELB
17 OEB
16 GND
15 GND
14 nCLK
13 CLK
ICS874005-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
IDT/ ICSPCI EXPRESS™ JITTER ATTENUATOR
1
ICS874005AG-04 REV. A JULY 29, 2008



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ICS874005-04 pdf
ICS874005-04
PCI EXPRESS™ JITTER ATTENUATOR
www.DataSheet4U.com
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 24
nQB2, QB2 Output
Differential output pair. LVDS interface levels.
2, 3 nQA1, QA1 Output
Differential output pair. LVDS interface levels.
4, 23
5, 6
7
8
VDDO
QA0, nQA0
MR
BW_SEL
Power
Output
Input
Input
Output supply pins.
Differential output pair. LVDS interface levels.
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inverted outputs
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pulldown PLL bandwidth input. See Table 3B. LVCMOS/LVTTL interface levels.
9
VDDA
Power
Analog supply pin.
10
F_SELA
Input
Pulldown
Frequency select pin for QAx/nQAx outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
11 VDD Power
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
12
OEA
Input Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels. See Table 3A.
13
CLK
Input Pulldown Non-inverting differential clock input.
14
nCLK
Input Pullup Inverting differential clock input.
15, 16
17
18
19, 20
GND
OEB
F_SELB
nQB0, QB0
Power
Input
Input
Output
Pullup
Pulldown
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels. See Table 3A.
Frequency select pin for QBx/nQBx outputs. See Table 3C.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
21, 22
nQB1, QB1 Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT/ ICSPCI EXPRESS™ JITTER ATTENUATOR
2
ICS874005AG-04 REV. A JULY 29, 2008



Part Number ICS874005-04
Description PCI EXPRESS JITTER ATTENUATOR
Maker Integrated Device Technology - Integrated Device Technology
Total Page 13 Pages
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