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ICS87001I-01

LVCMOS/LVTTL Clock Divider



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ICS87001I-01 pdf
LVCMOS/LVTTL Clock Divider
ICS87001I-01
DATA SHEET
General Description
The ICS87001I-01 is a low skew, ÷1, ÷2, ÷3, ÷4, ÷5, ÷6, ÷8, ÷16
LVCMOS/LVTTL Clock Divider. The ICS87001I-01 has selectable
clock inputs that accept single ended input levels. Output enable pin
controls whether the output is in the active or high impedance state.
The ICS87001I-01 is characterized at 3.3V, 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating
modes.Guaranteed part-to-part skew characteristics make the
ICS87001I-01 ideal for those applications demanding well defined
performance and repeatability.
Features
One LVCMOS / LVTTL output
Selectable LVCMOS / LVTTL clock inputs
Maximum output frequency: 250MHz
Part-to-part skew: 135ps (typical)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_SEL Pulldown
CLK0
Pulldown 0
CLK1
Pulldown 1
N2:N0 Pulldown
OE Pullup
3
N Output Divider
N2:N0
0 0 0 ÷1 (default)
0 0 1 ÷2
0 1 0 ÷3
0 1 1 ÷4
1 0 0 ÷5
1 0 1 ÷6
1 1 0 ÷8
1 1 1 ÷16
Q
Pin Assignment
OE
VDD
CLK0
CLK_SEL
CLK1
N2
N1
N0
1
2
3
4
5
6
7
8
16 VDDO
15 nc
14 Q
13 nc
12 GND
11 nc
10 nc
9 GND
ICS87001I-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
ICS87001BGI-01 REVISION A JANUARY 23, 2013
1
©2013 Integrated Device Technology, Inc.



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ICS87001I-01 pdf
ICS87001I-01 Data Sheet
LVCMOS/LVTTL CLOCK DIVIDER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
OE
Input
Pullup
Output enable. When LOW, output is in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
2 VDD Power
3, 5
CLK0, CLK1
Input
Pulldown
Power supply pin.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
4
CLK_SEL
Input
Pulldown
Input clock selection. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
6, 7, 8
N2, N1, N0
Input
Pulldown Output divider select pins. LVCMOS/LVTTL interface levels. See Table 3.
9, 12
GND
Power
Power supply ground.
10, 11, 13, 15
nc
Unused
No connect.
14 Q Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
16
VDDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
CPD
Power Dissipation
Capacitance
ROUT
Output Impedance
Test Conditions
VDDO = 3.465V
VDDO = 2.625V
VDDO = 1.95V
VDDO = 3.3V±5%
VDDO = 2.5V±5%
VDDO = 1.8V±0.15V
Minimum
Typical
4
51
51
6
5
5
17
20
28
Maximum
Units
pF
k
k
pF
pF
pF
Function Table
Table 3. Programmable Output Divider Function Table
Inputs
N2 N1 N0
000
001
010
011
100
101
110
111
N Divider Value
÷1 (default)
÷2
÷3
÷4
÷5
÷6
÷8
÷16
ICS87001BGI-01 REVISION A JANUARY 23, 2013
2
Maximum Output Frequency (MHz)
250
125
83.333
62.5
50
41.667
31.25
15.625
©2013 Integrated Device Technology, Inc.



Part Number ICS87001I-01
Description LVCMOS/LVTTL Clock Divider
Maker Integrated Device Technology - Integrated Device Technology
Total Page 14 Pages
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