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ICS854S058I

8:1 Differential-to-LVDS Clock Multiplexer



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8:1 Differential-to-LVDS Clock Multiplexer
ICS854S058I
DATASHEET
General Description
The ICS854S058I is an 8:1 Differential-to-LVDS Clock Multiplexer
which can operate up to 2.5GHz. The ICS854S058I has 8
selectable differential clock inputs. The PCLK, nPCLK input pairs
can accept LVPECL, LVDS, SSTL or CML levels. The fully
differential architecture and low propagation delay make it ideal for
use in clock distribution circuits. The select pins have internal
pulldown resistors. The SEL2 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 000 selects PCLK0, nPCLK0).
Features
High speed 8:1 differential multiplexer
One differential LVDS output pair
Eight selectable differential PCLK, nPCLK input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, SSTL, CML
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
Additive phase jitter, RMS: 0.065ps (typical)
Part-to-part skew: 300ps (maximum)
Propagation delay: 600ps (maximum)
Supply voltage range: 3.135V to 3.465V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
PCLK2 Pulldown
nPCLK2 Pullup/Pulldown
PCLK3 Pulldown
nPCLK3 Pullup/Pulldown
PCLK4 Pulldown
nPCLK4 Pullup/Pulldown
PCLK5 Pulldown
nPCLK5 Pullup/Pulldown
PCLK6 Pulldown
nPCLK6 Pullup/Pulldown
PCLK7 Pulldown
nPCLK7 Pullup/Pulldown
000
(default)
001
010
011
100
101
110
111
SEL2 Pulldown
SEL1 Pulldown
SEL0 Pulldown
Q
nQ
ICS854S058AGI REVISION A OCTOBER 29, 2012
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
1
2
3
4
5
6
7
8
9
10
11
12
24 PCLK7
23 nPCLK7
22 PCLK6
21 nPCLK6
20 VDD
19 Q
18 nQ
17 GND
16 PCLK5
15 nPCLK5
14 PCLK4
13 nPCLK4
ICS854S058I
24-Lead TSSOP, 173-MIL
7.8mm x 4.4mm x 0.925mm package body
G Package
Top View
1 ©2012 Integrated Device Technology, Inc.



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ICS854S058I pdf
ICS854S058I Datasheet
8:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 20
6, 7, 8
9
10
11
12
13
14
15
16
17
18, 19
21
22
23
24
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0,
SEL1,
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nPCLK4
PCLK4
nPCLK5
PCLK5
GND
nQ, Q
nPCLK6
PCLK6
nPCLK7
PCLK7
Input
Input
Input
Input
Power
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Input
Pulldown
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Input
Input
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Description
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Power supply ground.
Differential output pair. LVDS interface levels.
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Non-inverting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RVDD/2
Parameter
Input Capacitance
Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
75
50
Maximum
Units
pF
k
k
ICS854S058AGI REVISION A OCTOBER 29, 2012
2
©2012 Integrated Device Technology, Inc.



Part Number ICS854S058I
Description 8:1 Differential-to-LVDS Clock Multiplexer
Maker Integrated Device Technology - Integrated Device Technology
Total Page 16 Pages
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