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ICS854S057BI

4:1 or 2:1 LVDS Clock Multiplexer



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ICS854S057BI pdf
4:1 or 2:1 LVDS Clock Multiplexer with
Internal Input Termination
ICS854S057BI
DATA SHEET
General Description
The ICS854S057BI is a 4:1 or 2:1 LVDS Clock
ICS Multiplexer which can operate up to 2GHz. The PCLK,
HiPerClockS™ nPCLK pairs can accept most standard differential
input levels. Internal termination is provided on each
differential input pair. The ICS854S057BI operates
using a 2.5V supply voltage. The fully differential architecture and
low propagation delay make it ideal for use in high speed
multiplexing applications. The select pins have internal pulldown
resistors. Leaving one input unconnected (pulled to logic low by the
internal resistor) will transform the device into a 2:1 multiplexer. The
SEL1 pin is the most significant bit and the binary number applied to
the select pins will select the same numbered data input (i.e., 00
selects PCLK0, nPCLK0).
Features
High speed differential multiplexer. The device can be configured
as either a 4:1 or 2:1 multiplexer
One LVDS output pair
Four selectable PCLK, nPCLK inputs with internal termination
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2GHz
Part-to-part skew: 200ps (maximum)
Propagation delay: 800ps (maximum)
Additive phase jitter, RMS: 0.065ps (typical)
Full 2.5V power supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
VT0
50
PCLK0
nPCLK0
VT1
50
50
PCLK1
nPCLK1
50
VT2
50
PCLK2
nPCLK2
VT3
50
50 50
PCLK3
nPCLK3
SEL1 Pulldown
SEL0 Pulldown
00
01
10
11
Q
nQ
ICS854S057BGI REVISION A MARCH 29, 2010
Pin Assignment
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
1
2
3
4
5
6
7
8
9
10
20 VDD
19 PCLK3
18 VT3
17 nPCLK3
16 Q
15 nQ
14 PCLK2
13 VT2
12 nPCLK2
11 GND
ICS854S057BI
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
Top View
1 ©2010 Integrated Device Technology, Inc.



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ICS854S057BI pdf
ICS854S057BI Data Sheet
4:1, OR 2:1 LVDS CLOCK MULTIPLEXER W/INTERNAL INPUT TERMINATION
Table 1. Pin Descriptions
Number
1, 20
2
3
4
5, 6
7
8
9
10, 11
12
13
14
15, 16
17
18
19
Name
VDD
PCLK0
VT0
nPCLK0
SEL1, SEL0
PCLK1
VT1
nPCLK1
GND
nPCLK2
VT2
PCLK2
nQ, Q
nPCLK3
VT3
PCLK3
Type
Power
Input
Input
Input
Input Pulldown
Input
Input
Input
Power
Input
Input
Input
Output
Input
Input
Input
Description
Power supply pins.
Non-inverting LVPECL differential clock input. RT = 50termination to VT0.
Termination input. For LVDS input, leave floating. RT = 50termination to VT0.
Inverting LVPECL differential clock input. RT = 50termination to VT0.
Clock select inputs. LVCMOS/LVTTL interface levels.
Non-inverting LVPECL differential clock input. RT = 50termination to VT1.
Termination input. For LVDS input, leave floating. RT = 50termination to VT1.
Inverting LVPECL differential clock input. RT = 50termination to VT1.
Power supply ground.
Inverting LVPECL differential clock input. RT = 50termination to VT2.
Termination input. For LVDS input, leave floating. RT = 50termination to VT2.
Non-inverting LVPECL differential clock input. RT = 50termination to VT2.
Differential output pair. LVDS interface levels.
Inverting LVPECL differential clock input. RT = 50termination to VT3.
Termination input. For LVDS input, leave floating. RT = 50termination to VT3.
Non-inverting LVPECL differential clock input. RT = 50termination to VT3.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLDOWN Input Pulldown Resistor
RT Input Termination Resistor
Test Conditions
Table 3. Control Input Function Table
Inputs
SEL1
SEL0
00
01
10
11
Outputs
PCLKx, nPCLKx
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK2, nPCLK2
PCLK3, nPCLK3
Minimum
40
Typical
2
50
50
Maximum
60
Units
pF
k
ICS854S057BGI REVISION A MARCH 29, 2010
2
©2010 Integrated Device Technology, Inc.



Part Number ICS854S057BI
Description 4:1 or 2:1 LVDS Clock Multiplexer
Maker Integrated Device Technology - Integrated Device Technology
Total Page 15 Pages
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