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ICS8545-02

1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER


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ICS8545-02 pdf
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS
FANOUT BUFFER
ICS8545-02
Description
The ICS8545-02 is a low skew, high performance
ICS 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout
HiPerClockS™ Buffer and a member of the HiPerClockS™ family of
High Performance Clock Solutions from IDT.
Utilizing Low Voltage Differential Signaling (LVDS)
the ICS8545-02 provides a low power, low noise, solution for
distributing clock signals over controlled impedances of 100. The
ICS8545-02 accepts an LVCMOS/LVTTL input level and translates
it to 3.3V LVDS output levels.
wwGwua.DraantateSehdeeotu4tUp.uctoamnd part-to-part skew characteristics make the
ICS8545-02 ideal for those applications demanding well defined
performance and repeatability.
Features
Four differential LVDS output pairs
Two LVCMOS/LVTTL clock inputs to support redundant
or selectable frequency fanout applications
Maximum output frequency: 350MHz
Translates LVCMOS/LVTTL input signals to LVDS levels
Output skew: 60ps (maximum)
Part-to-part skew: 450ps (maximum)
Propagation delay: 1.45ns (maximum)
Additive phase jitter, RMS: 0.14ps (typical)
Full 3.3Vsupply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK_EN Pullup
CLK1 Pulldown
CLK2 Pulldown
CLK_SEL Pulldown
00
11
nD
Q
LE
OE Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
GND
CLK_EN
CLK_SEL
CLK1
nc
CLK2
nc
OE
GND
VDD
1
2
3
4
5
6
7
8
9
10
20 Q0
19 nQ0
18 VDD
17 Q1
16 nQ1
15 Q2
14 nQ2
13 GND
12 Q3
11 nQ3
ICS8545-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
IDT™ / ICS™ LVDS FANOUT BUFFER
1
ICS8545AG-02 REV. A March 3, 2009



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ICS8545-02 pdf
ICS8545-02
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 9, 13
2
3
Name
GND
CLK_EN
CLK_SEL
Type
Power
Input
Pullup
Input Pulldown
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK2 input.
When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels.
4
CLK1
Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
5, 7 nc
6 CLK2
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10, 18
11, 12
14, 15
16, 17
19, 20
VDD
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
Unused
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pullup
No connect.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
IDT™ / ICS™ LVDS FANOUT BUFFER 2 ICS8545AG-02 REV. A March 3, 2009



Part Number ICS8545-02
Description 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Maker Integrated Device Technology - Integrated Device Technology
Total Page 13 Pages
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