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ICS853S54I

Differential-to-LVPECL/ECL Multiplexer


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ICS853S54I pdf
Dual 2:1, 1:2 Differential-to-LVPECL/ECL
Multiplexer
ICS853S54I
DATA SHEET
General Description
The ICS853S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplex-
er allows one of 2 inputs to be selected onto one output pin and the
1:2 MUX switches one input to one of two outputs. This device is
useful for multiplexing multi-rate Ethernet PHYs which have 100 M
bit and 1000 bit transmit/receive pairs onto an optical SFP module
which has a single transmit/receive pair. See Application Section for
further information.
The ICS853S54I is optimized for applications requiring very high
performance and has a maximum operating frequency of 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
Three differential LVPECL output pairs
Three differential LVPECL clock inputs
PCLKx/nPCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, CML
Maximum output frequency: 2.5GHz
Part-to-part skew: 200ps (maximum)
Propagation delay: QA, nQA: 450ps (maximum)
QBx, nQBx: 420ps (maximum)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packageing
Block Diagram
CLK_SELA Pulldown
PCLKA0 Pulldown
nPCLKA0 Pullup/Pulldown
PCLKA1 Pulldown
nPCLKA1 Pullup/Pulldown
PCLKB Pulldown
nPCLKB Pullup/Pulldown
CLK_SELB Pulldown
0
QA
nQA
1
QB0
nQB0
QB1
nQB1
Pin Assignment
16 15 14 13
QB0 1
12 PCLKA0
nQB0 2
11 nPCLKA0
QB1 3
10 PCLKA1
nQB1 4
9 nPCLKA1
5 6 78
ICS853S54I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS853S54AKI REVISION A OCTOBER 30, 2012
1
©2012 Integrated Device Technology, Inc.



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ICS853S54I pdf
ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
3, 4
5
6
7
8
9
10
11
12
13
14
15, 16
Name
QB0, nQB0
QB1, nQB1
PCLKB
nPCLKB
CLK_SELB
VEE
nPCLKA1
PCLKA1
nPCLKA0
PCLKA0
VCC
CLK_SELA
nQA, QA
Type
Output
Output
Input
Pulldown
Input
Pullup/
Pulldown
Input
Pulldown
Power
Input
Input
Input
Input
Power
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Input
Pulldown
Output
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Non-inverting LVPECL/ECL differential clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Clock select pin for QBx outputs. When HIGH, selects QB1/nQB1 outputs.
When LOW, selects QB0/nQB0 outputs. LVCMOS/LVTTL interface levels.
Negative supply pin.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Non-inverting LVPECL/ECL differential clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Non-inverting LVPECL/ECL differential clock input.
Positive supply pin.
Clock select pin for QA output. When HIGH, selects QA output. When LOW,
selects nQA output. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RVCC/2
Parameter
Input Capacitance
Input Pullup Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
37.5
37.5
Maximum
Units
pF
k
k
Function Tables
Table 3A. Control Input Function Table, (Bank A)
Bank A
Control Input
Outputs
CLK_SELA
QA, nQA
0 (default)
Selects PCLKA0, nPCLKA0
1 Selects PCLKA1, nPCLKA1
Table 3B. Control Input Function Table, (Bank B)
Bank B
Control Input Outputs
CLK_SELB QB0, nQB0
QB1, nQB1
0 (default) Follows PCLKB input Logic Low
1 Logic Low
Follows PCLKB input
ICS853S54AKI REVISION A OCTOBER 30, 2012
2
©2012 Integrated Device Technology, Inc.



Part Number ICS853S54I
Description Differential-to-LVPECL/ECL Multiplexer
Maker IDT - IDT
Total Page 21 Pages
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